====================================================================
File Name       : pfr_dnp_10M50_v5p4.pof
Version     	: v5p4
Version type	: Normal
Date            : 2024/10/18
Checksum        : 

[Add/Change]
1. Version change to 0x36 DNP v5p4, mailbox and SGPIO.

2.- SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
  - ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Fix HSD 14019939026: BMC Critical Event Intel ME has detected SMBus link error 
   Sensor Bus SmLink1 MUX Address 0xFF
   >> add "774.3pfr" file to fix this issue.
====================================================================
File Name       : pfr_dnp_10M50_v5p2.pof
Version     	: v5p2
Version type	: Normal
Date            : 2024/05/02
Checksum        : 

[Add/Change]
1. Version change to 0x34 DNP v5p2, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Remove "HSD 14019939026: BMC Critical Event Intel ME has detected SMBus link
   error Sensor Bus SmLink1 MUX Address 0xFF" issue solution
====================================================================
File Name       : pfr_dnp_10M50_v5p0.pof
Version     	: v5p0
Version type	: Normal
Date            : 2024/04/11
Checksum        : 

[Add/Change]
1. Version change to 0x32 DNP v5p0, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Fix HSD 14019939026: BMC Critical Event Intel ME has detected SMBus link error
   Sensor Bus SmLink1 MUX Address 0xFF

4. Delay PLTRST to 1 second to fix DNP ACCL card lost issue
====================================================================
File Name       : pfr_dnp_10M50_v4p8.pof
Version     	: v4p8
Version type	: Normal
Date            : 2024/01/02
Checksum        : 

[Add/Change]
1. Version change to 0x30 DNP v4p8, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Fix BIOS recovery will be triggered after updating BMC OnReset for a while
====================================================================
File Name       : pfr_dnp_10M50_v4p6.pof
Version     	: v4p6
Version type	: Normal
Date            : 2023/09/11
Checksum        : 

[Add/Change]
1. Version change to 0x30 DNP v4p6, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Only bring down BMC if only BMC active firmware is being updated
====================================================================
File Name       : pfr_dnp_10M50_v4p4.pof
Version     	: v4p4
Version type	: Normal
Date            : 2023/06/13
Checksum        : 

[Add/Change]
1. Version change to 0x30 DNP v4p4, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Change the reference signal of PSU to P12V_BOARD_PWRGDYUA to fix the problem
   that CBB 48V is turned on under S5
====================================================================
File Name       : pfr_dnp_10M50_v4p2.pof
Version     	: v4p2
Version type	: Normal
Date            : 2023/05/09
Checksum        : 

[Add/Change]
1. Version change to 0x30 DNP v4p2, mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. SMBUS Filter Relay : OAM SKU verify issue with BMC v1.59 and CPLD v4P2.
    3.1 Import RP_team to correct the condition of timeout.
    3.2 Added below logic in pfr_core.sv file (attached) to reset the
        smbus_filter_relay whenever BMC is reset.
    3.3 When smbus realy hang over 3 sec , smbus will be reset myself.
====================================================================
File Name       : pfr_dnp_10M50_v4p0.pof
Version     	: v4p0
Version type	: Normal
Date            : 2023/03/01
Checksum        : 

[Add/Change]
1. Version change to 0x28 DNP v4p0), mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed (mailbox 0x02), 0x08 for Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Add/remove spi whitelist.01h/35h/B1h/B5h add to whitelsit;
   35h/B1h remove to forbidden list.spi_filter.sv
   [2103657177] System don't power on automatically if set "Power on" in BIOS
   setting "Resume on AC power loss" with Winbond BMC SPI flash.
4. Remove RP code 475p4, about WDT recovery/implementing FIFO for IBB/OBB
   checkpoints which are related to Bios rollback conditions.
   -FW 
     t0_watchdog_handler.h
   -RTL 
     1. path: reg_file.sv / fifo.sv / platform_def_pkg.sv
====================================================================
File Name       : pfr_dnp_10M50_v3p8.pof
Version     	: v3p8
Version type	: Normal
Date            : 2023/02/16
Checksum        : 

[Add/Change]
1. Version change to 0x26(DNP v3p8), mailbox and SGPIO.

2. SVN value is 0x02 for Debug Signed (mailbox 0x02), 0x08 fpr Production Signed.
   ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Reset i2c MM5 bus when bus fail, and output the signal with SGPIO to tell BMC that CPLD has reset the bus. 
   BMC send clear bit to CPLD with sgpio, clear bit "75"
	-MM5 fail, bit "75" pull high tell BMC need to rest their bus.
	-wBmcSgpioRsrvd[31] pull high, bit 75 pull down.
    - [2103654938][p3-medium][open] [DNP LC OAM] OAM OAM CBB_OAMX_PVC FRU and SDR lost during DC cycling.

4. -Add new RP code, about WDT recovery/implementing FIFO for IBB/OBB checkpoints which are related to Bios rollback conditions.
	-Add IBB, OBB checkpoint Fifo implementation.
	-Swap control status register with bios fifo 0x6A and 0x6B
	-implement new fifo for ibb and obb checkpoint 
	-add block level simulation test to validate the fifo for bios checkpoint and enable this test in cabbage build

       -FW 344p4 upgrade to 475p4
        1. path: mailbox_enums.h / t0_routines.h / t0_update.sv / i2c_update.h / transition.h / t0_watchdog_handler.h
       -RTL 344p4 upgrade to 475p4
        1. path: reg_file.sv / fifo.sv / platform_def_pkg.sv
     -[15012107629][SH ST][FCP][DNP]The Bios roll back to backup version during reset test.
====================================================================
File Name       : pfr_dnp_10M50_v3p6.pof
Version     	: v3p6
Version type	: Normal
Date            : 2023/01/13
Checksum        : 

[Add/Change]
1. Version change to 0x24 (DNP v3p6), mailbox and SGPIO.

2. - SVN value is 0x02 for Debug Signed (mailbox 0x02), 0x08 for Production Signed.
   - ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. - Delay get into T minus one mode timing for 2 second .
   - [HSD]PXE/HTTP boot options of onboard NIC will disappear randomly on Setup UI after flash BIOS via sysfwupdt.efi

4. - Changed the system CLK down to 20M Hz.
   - [HSD] The BMC automatically downgraded to backup version.

5. - Add reset WDT Timer function in "mailbox_enums.h" file.
   - Add restart OBB WDT timer for retimer fw update function in "t0_watchdog_handler.h" file.
   - [2103655983] CPLD will trigger OBB timeout when updating RTM FW over 25 minutes.

6. - U.2 Riser IFDetect two pins seperate to controller 1 and 2, riser 1 for CPU1, riser 2 for CPU0. 
   - [HSD] DNP_S2EG2SE3HB_99C7M2, UT did not install SSD in Riser 1 slot 3, but display.cfg shows that SSD can be found in riser 1 slot 3.
====================================================================
File Name       : pfr_dnp_10M50_v3p4.pof
Version     	: v3p4
Version type	: Normal
Date            : 2022/11/25
Checksum        : 

[Add/Change]
1. Version change to 0x22(DNP v3p4), mailbox and SGPIO.

2. - SVN value is 0x02 for Debug Signed (mailbox 0x02), 0x08 fpr Production Signed.
   - ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 for Whitley.

3. Add FM_RISER1_U2_IFDET_N / FM_RISER2_U2_IFDET_N in AGPIO mapping. At sgpio 77, 76.
	>> HSD [2103656179][DNP] The NVMe SSD Information doesn't disappear in EWS after remove U.2 device.

====================================================================
File Name       : pfr_dnp_10M50_v3p2.pof
Version     	: v3p2
Version type	: Normal
Date            : 2022/10/31
Checksum        : 

[Add/Change]
1. The 12V stand by power will drop down to 11V when power on instantly, because "FM_AUX_SW_EN" pull high too fast.
   We delay "FM_AUX_SW_EN" for 20ms.

2. SVN = 2. ROT version = 2.
====================================================================
File Name       : pfr_dnp_10M50_v3p0.pof
Version     	: v3p0
Version type	: Normal
Date            : 2022/10/31
Checksum        : 

[Add/Change]
1. The BMC automatically downgraded to backup version (HSD-15011479469).
  - We follow FCP take SPI clock down to 40Mz avoid to SPI CS# signal abnormal.

2. LAN can't work of DHCP IP address and share port after CPLD update.  (HSD-15011789377 / HSD-2103654680 )
   - Modify BMC power on sequence to delay 200msec form 1.2V power good to 1.0V.

3. SVN = 2. ROT version = 2.

====================================================================
File Name       : pfr_dnp_10M50_v2p8.pof
Version     	: v2p8
Version type	: Normal
Date            : 2022/09/15
Checksum        : 

[Add/Change]
1. add pass3 CBB FRU address 0x56 in white list.

2. BMC Status is abnormal after online flash BMC with sysfwupdt.efi v16.0 (HSD-2103647183)
   - Update behavior PCH hold reset when BMC is online update 
note :path:fw\code\hw\archer_city\Makefile,line 155  APP_CFLAGS_USER_FLAGS += -DDSG_EGS_HSD_2103647183

3. SVN = 2. ROT version = 2.

====================================================================
File Name       : pfr_dnp_10M50_v2p6.pof
Version     	: v2p6
Version type	: Normal
Date            : 2022/07/28
Checksum        : 

[Add/Change]
1.Improve FRB2 behavior for CCB3611
   - Delete ACM/BIOS watchdog timer check in t0_routines.h because the currently is inactive. 
2. FM_SVN_BYPASS exchange FM_BIOS_SVN_DOWNGRADE_R pin loacation.
   - FM_SVN_BYPASS Change from original J14 to L15
3. I2C rule change address on CBB 
   - Modify SMBUS relay 3 address in gen_smbus_relay_config.h and gen_smbus_relay_config_pkg.sv.
4. Version changes to 0x1A (DNP v2p6)
   - Modify "MB_CPLD_COMMON_CODE_VER_VALUE" value in mailbox_enums.h  (\fw\code\inc)
   - Modify "FPGA_REV" value in DNP_Parameter.def (\src\core_cpld)
5. SVN = 2. ROT version = 2.
   - SVN value is 0x02 for Debug Signed(mailbox 0x02), 0x01 is Production Signed
   - ROT vlaue is 0x02 for EagleStream PLATFORM (mailbox 0x03), 0x01 is Whitley
6. Start with BMC version "egs-1.21-0", it will match the CPLD v2p6 which change the I2c rule address.

====================================================================
File Name       : pfr_dnp_10M50_v2p4.pof
Version     	: v2p4
Version type	: Normal
Date            : 2022/06/17
Checksum        : 

[Add/Change]
1. Change ECDSA module and QSPI frequency and system clock up to 40Mhz.
   - PLL C1 output change to 40Mhz and C2 change to 80Mhz.
   - add crypto_multr_all.sv module to improve performance in ecdsa384.sv and ecdsa256_top.v. 
2. When PFR is enable CPLD support 64K erase command for BIOS image.
   -add SPI_CMD_SECTOR_ERASE bios flash command in spi_filter.sv
3. SVN = 2. ROT version = 2.

====================================================================
File Name       : pfr_dnp_10M50_v2p2.pof
Version     	: v2p2
Version type	: Normal
Date            : 2022/05/20
Checksum        : 

[Add/Change]
1. Porting 256.3 New NIOS code (EGS_PLD_256.3_WW12) implement the new format (mailbox register 0x7E /0X7F , SGPIO BYTE 5)
2. Modify  perform_platform_reset () to perform_bmc_only_reset() in “ t0_update.h “ file to fix SUT doesn't power on automatically after update BMC via sysfwupdt
3. SMBUS MM[9] address because conflict PCIE_SMBUS_MAILBOX_ADDR address 0x70 change to 0x38  
4. Sync DIMM Power Fail signal and modify DIMM reset behavior to fix timing issue.
5. SVN = 1. RoT version = 2.

====================================================================
File Name       : pfr_dnp_10M50_v2p0.pof
Version     	: v2p0
Version type	: Normal
Date            : 2022/03/23
Chacksum        : 

[Add/Change]

1.Update fw_patched_193.4-220224 code.
2.Update HSD 2103649051 issue.
-->adr_fub.v file INIT status add P12V_BOARD_PWRGD confirm.
3.Update EGS_PLD_256.3_WW12 for RTL Source code.
4.add OAM MCTP endpoint address 7h’58/8h’B0 ,in the i2c Bus relay3 (MM5) num addresses =22 .
5.CBB /U14(MUX) address 0xE0 change to 0xeE6  ,in the i2c Bus relay3 (MM5) num addresses =3 .
6.Synchronous smbus address for BMC FW rev: 0.99.
7.SVN = 2. RoT version = 2.

Supplementary Instructions,item 8 and 9
8.whitelist CBB /U14(MUX) address 0xE0 for EE request add ,include in "DNP_10M50_V1P6"version.
9.OAM Power sequence,include in "DNP_10M50_V1P6"version.
10.The 10M25 stays in the Fab2 version, and the BIOS and BMC SVN functions cannot be downgraded without the Fab3 version.
   10M50 Fab3 and later versions can downgrade SVN function.( in Activer & Recovery Region downgrade SVN.)
   (command used sysfwupdt.efi -u -recovery bios_previous_ver_capsule.bin ImmReset)

====================================================================
File Name       : pfr_dnp_10M50_v1p8.pof
Version     	: v1p8
Version type	: Normal
Date        	: 2022/02/17
Chacksum        : 

[Add/Change]

1.Add PCH and BMC SVN downgrade feature, DSG_EGS_JIRA_DSSGP_136.
2.whitelist BMC slave address modify 0x12 for BMC request.
3.Change PERST_N from CPU_PWRGD to PLTRST_N.
4.FM_SYS_THROTTLE_N delete not gate for DNP.
5.Drive relay all address back to 0 during provisioning.
6.Enable CPLD attestation so modify APP_CFLAGS_UNDEFINED_SYMBOLS += -UENABLE_ATTESTATION_WITH_ECDSA_384
in the makefile.
7.to solve the lower frequency caused the PSU timeout issue, so update SYS clock from 33333 to 50000.

====================================================================
File Name       : pfr_dnp_10M50_v1p6.pof
Version     	: v1p6
Version type	: Normal
Date        	: 2022/01/26
Chacksum        : 0B39A17D

[Add/Change]

v1.MCTP MM5 set 1
v2.BMC slave address 0x24 for MM5 BUS
v3.Modify crypto_dma module for BMC authentication fail at ac cycle case.
v4.modify SPGIO
v5.intel source code 193.4(ddr issue)
v6.NVME LED control and VPP I2C pin 
v7.EE NEW request modify PCIe device reset
v8.update C code for the RAM region of NIOS.

====================================================================
File Name       : pfr_dnp_10M50_v1p4.pof
Version     	: v1p4
Version type	: Normal
Date        	: 2021/12/6
Chacksum        : 0B67C286

[Add/Change]
1. Customer's requirements and suggestions for version updates.
2. The new requirement of EE, changed from RST_PLTRST_PLD_N to PWRGD_CPUx_LVC1.

====================================================================
File Name       : pfr_dnp_10M50_v0p1.pof
Version     	: v0p1
Version type	: Normal
Date        	: 2021/11/26
Chacksum        : 0B83477F

[Add/Change]
1. First Release of PFR Feature.

====================================================================







