================================================================================ DATE : TO : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers SUBJECT : BIOS Release notes ================================================================================ LEGAL INFORMATION ================================================================================ Information in this document is provided in connection with Intel Products and for the purpose of supporting Intel developed server boards and systems. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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Copyright (C) Intel Corporation. ================================================================================ ABOUT THIS RELEASE ================================================================================ Build Stamp: SE5C620.86B.01.01.0010.2501091858 Build Date: Jan. 9, 2025 ================================================================================ Supported Platforms ================================================================================ CoyotePass R01010010_CoyotePass_LBG_ICX_prd.bin Checksum: 0x598B9443 SFID offset: 0x7B8024 SFID value: 0x65388bf7 TennesseePass R01010010_TennesseePass_LBG_ICX_prd.bin Checksum: 0x59867720 SFID offset: 0x7B8024 SFID value: 0x27e6f454 ================================================================================ BIOS COMPONENTS/CONTENTS ================================================================================ Processors supported: Xeon Scalable Family Processor Microcode versions: CPUID Version Status 606a4 0x0b000280 (ICX-SP HCC L0) 606a5 0x0c0002f0 (ICX-SP XCC C0) 606a6 0x0d0003e7 (ICX-SP XCC D0/D1/D2 & HCC M1) SATAAHCI: v2.00i VROCSataEfi: v8.5.0.1096 VROCsSataEfi: v8.5.0.1096 BIOSACM: Production,v1.3.7_LBG SINIT: Production,v1.3.8_LBG NvmDimmDriver: v02.00.00.3887 NvmDimmHii: v02.00.00.3887 ASTVBIOS: v1.09 VMDVROC2: v8.5.0.1096 VMDVROC1: v8.5.0.1096 SPS: 04.04.04.603 PCH PFR SVN: 03 ================================================================================ INSTALLATION NOTES ================================================================================ WARNING: It is very important to follow these instructions as they are written. Failure to update using the proper procedure may cause damage to your system. Firmware Update Tools: Sysfwupdt User can update BIOS flash image via UEFI sysfwupdt. See 'Readme and Update Instructions.txt' ================================================================================ SVN_BYPASS Jumper ================================================================================ Using the SVN_BYPASS Jumper to flash to a lower SVN: 1. Remove AC power 2. Switch the SVN_BYPASS jumper. The jumper ID and location are listed in the board TPS. 3. Power on the system, and boot to the BIOS setup. 4. At Main->PFR page, check "PCH SVN Bypass Jumper Status: ON". 5. Boot to the uEFI shell, and downgrade the BIOS by command: sysfwupdt.efi -u xxx.bin -recovery. ================================================================================ IMPORTANT NOTICE ================================================================================ - If you are on BIOS R01.01.0007 or earlier, update to CPLD v4p7 included with the BIOS R01.01.0008 package first. Reboot, then apply the rest of the BIOS R01.01.0008 package. Then you can update to R01.01.0009 or R01.01.0010 - BIOS R01.01.0010 requires new secure boot keys for Microsoft Windows 2025: KEK – Microsoft Corporation KEK 2K Certificate Authority (CA) 2023*. DB – Windows UEFI CA 2023*, Microsoft UEFI CA 2023* and Microsoft Option ROM UEFI CA 2023*. To update the new KEK and DB keys, the previous secure boot keys stored in BIOS must be removed via the "UpdateNvram" parameter, via SUP (UEFI) or SFUP (Windows/Linux) update packages. The 'UpdateNvram' parameter can not be used, if updating the BIOS via the BMC Embedded Web Server (EWS). If using SUP/UEFI, modify the UpdBIOS_CYP.nsh script from sysfwupdt.efi -u R01010010_CoyotePass_LBG_ICX_UpdateCapsule_prd.bin ImmReset to sysfwupdt.efi -u R01010010_CoyotePass_LBG_ICX_UpdateCapsule_prd.bin ImmReset+UpdateNvram If using SFUP/WINLNX, modify the bios_update.sh from BIOS="R01010010_CoyotePass_LBG_ICX_UpdateCapsule_prd.bin -recovery" to BIOS="R01010010_CoyotePass_LBG_ICX_UpdateCapsule_prd.bin -recovery UpdateNvram" This will also restore all BIOS settings to default values. The above parameter is only necessary if you are using Microsoft Windows 2025. Other operating systems will not require these steps. ================================================================================ KNOWN ISSUES/WORKAROUND ================================================================================ 1.[Hsd-ES]:[2103628066] Windows 2019 will BSOD when enable VT-D.Please enable "Limit CPU PA to 46 bits" when boot to Windows 2019 with Intel(R) VT for Directed I/O enabled. 2.[Hsd-ES]:[1509669610] There is one critical "Force ME Recovery" event in SEL after online flash BIOS from R01010003 to later version via sysfwupdt.efi(regression issue) W/A: Update BIOS with UpdateNvram pamrameter. e.g. sysfwupde.efi -u xxx.bin UpdateNvram 3.[Hsd-ES]:[16015331615] Prompt message appears when online update BIOS from R01010004 to later with ASPM is "L1 only" setting. W/A:Online update BIOS by UpdateNvram parameter or press F9 after online update BIOS. 4.[Hsd-ES]:[2103646748] 'PPR' option default setting is disabled after online flash BIOS from R01010004 to later. W/A:Online update BIOS by UpdateNvram parameter or press F9 after online update BIOS. 5.[Hsd-ES]:[2103647928] [MiTAC] Enter Windows2022 OS and inject UCE, there are many unexpected log for 'OEM timestamped' and 'Event type 6f, offset 1' generated. 6.[Hsd-ES]:[2103647907][Whitley][CYP/TNP]Downgrade SUP or FSUP from Can2 release to R004 or R0003 , system will report SPS FW Health error in sellog. W/A:1. Downgrade SUP or FSUP with UpdateNvram when flash BIOS 2. AC off, set ME jumper to force recovery mode first, AC on boot system then AC off and set ME jumper to normal. 3. using IPMI command to force ME recovery mode: ipmitool.exe -H x.x.x.x(BMC IP) -U xxx(BMC User name) -P xxxx(BMC User password) -I lanplus -b 6 -t 0x2c raw 0x2e 0xdf 0x57 1 0 2 7.[Hsd-ES]:[2103648506] [MiTAC] System will halt at POST and report 'IERR-Non boot core FIVR fault' in sel after set disable CPU core No. with IPMI command. 8.[Hsd-ES]:[2103651639] [MiTAC] Offline flash R01010005 BIOS of SVN 02 then downgrade to R01010003 of SVN1, after that system is unable to flash the same SVN BIOS(R0004) again 9.[Hsd-ES]:[15011179840] [Whitley][CYP]Aurora - Boot order change after upgrading BIOS from R01011003 to R005 10.[Hsd-ES]:[2103644614] [MiTAC]One "Serial Port B" option listed under EWS -> BIOS Configurations -> Server Management -> Console Redirection 11.[Hsd-ES]:[2103652728] [CYP/TNP][MiTAC]There are many settings under EWS Integrated IO configuration page(About 497),which does not see in BIOS setup. 12.[Hsd-ES]:[15011339171] SGX registration failed when downgrade BIOS to R0006. W/A: Goto Advanced->Processor Configuration page, set "SGX Factory Reset" to Enable, after reset the problem will fix. 13.[Hsd-ES]:[2103654290] [MiTAC] Error is prompted when create RAID volume if enable pre-boot DMA protection option 14.[Hsd-ES]:[2103655351] [MiTAC] Offline flash R01010006 then online update to 0028P01 BIOS, the 'Custom Refresh Rate' default value is 0. 15.[Hsd-ES]:[2103659097] [MiTAC] After clear customized setting and load BIOS default, the BIOS stup options still keep ITK setting of 'Show' feature's value. ================================================================================ CHANGE LIST ================================================================================ R01010010 ================================================================================ [BTS]:[48329]: CpPcPlatPkg\SecureBootKeys: Secure Boot Logo Test Fail.(windows 2025,BIOS_R0009). [CCB]:[4837]: [Whitley] [BIOS] Integrate fix for CVE-2021-38578 into QSBR BIOS. Server-RC-0.4.2.0038 Update CVE Fixes. 2024-24968 (DocID: 817568) 2024-24853 (DocID: 819098) 2024-23984 (DocID: 817900) 2024-24980 (DocID: 817884) 2024-21820 (DocID: 815946) 2024-23918 (DocID: 815946) 2024-21829 (DocID: 815853) 2024-21781 (DocID: 815853) 2023-43753 (DocID: 815853) 2024-32050 2024-31157 2024-28047 2024-21859 2024-22382 2024-24971 2024-23980 2024-24981 2024-22095 This release is mapping to RP release Reference code version: WHITLEY.0.RPB.0030.P.47 (Whitley_IPU/2024.3) [CCB]:[4833][HSD]:[15015119190] [Whitley][BIOS]Please disable MCTP for Whitley. [HSD]:[2103661913] The "Connector Type" show incorrect under EWS->System->"Storage information" interface when set "VMD Enabled" in BIOS with Micron 7450 PRO 3.84T M.2-22110. [HSD]:[15016202325] Changing BIOS knob of 'Data Link Feature Exchange' for CPU1 2A~2D doesn't apply to CYP 1U/Riser slot#2. [HSD]:[2103659138] System will auto reset deadloop after modify “Reset PCI Rebalance Data” option to Enable and save in EWS OOB BIOS update. [HSD]:[15012894713] [Whitley-M50CYP][BIOS-ME]IPS05745549 ME crash issue. [CCB]:[4839] [BIOS]Please Include IPU2024.1 to Whitley BIOS. [IPU2024.1][HSD]:[14019386021] Revert "Requests new Advanced MemTest Test Type 20 for DDR4" [IPU2024.1][HSD]:[16020901470] BIOS SHALL update the DFX SAI_PG of the memory controllers to mitigate security exploits. [IPU2024.1][HSD]:[15013443915] BIOS SHALL update the DFX SAI_PG of the memory controllers to mitigate security exploits. [IPU2024.1][HSD]:[14019800028] PCIe Reporting (PCIe Error SMM Handler) doesn't function correctly under massive CE condition. Error Triggered SMI generation stopped. [IPU2024.1][HSD]:[14019385344] Add new pattern for memtest type 16 to strengthen the AMT PPR [IPU2024.1][HSD]:[14019230848] Invalid DIMM SPD CRC Causes Fatal Error (or Boot Loop and Inoperable System). [IPU2024.1][HSD]:[14019253026] AMT Memtest type 17 report false failure when 8Gb and 16Gb know bad DIMMs are present. [IPU2024.1][HSD]:[18030509126] SGX Registration Protocol shall introduce user controlled 'read-only' mode [IPU2024.1][HSD]:[18029869387] SGX Support - BIOS shall implement ICX CPU BWG 0.50 - 1.8.5.10 Configure PRMRRs - also supporting dynamic PCIe MMCFG base (1GB-3GB). [IPU2024.1][HSD]:[22018341284] Retire Descriptor Tool in Gen1 Programs. [IPU2024.1][HSD]:[14019403457] Adding Manufacturer ID Codes for Longsys. [IPU2024.1][HSD]:[16019943714] PCH PCI-E RAS error reporting only occurs 1st time but fail then. [IPU2024.1] Update XCC Production Microcode D0/D1/D2/HCC M1 m87_606a6_0d0003d1 [IPU2024.1] Update ME version to E5_04_04_04_603 [CCB]:[4844] [BIOS]Please Include IPU2024.3 to Whitley BIOS. [IPU2024.3][HSD]:[14021394982] Ensure SWSMI gets reinstataed before exiting the function. [IPU2024.3][HSD]:[14021389121] Revert "Fix support for SMM in IIO API library". [IPU2024.3][HSD]:[14021239042] Update AMT with test type 21 support. [IPU2024.3][HSD]:[22019088009] Support RP IFWI generation without FlashImageTool. [IPU2024.3][HSD]:[22019333705] SGX Registration Protocol shall introduce user controlled 'read-only' mode - Remove SgxUefiRegistrationResponse variable. [IPU2024.3][HSD]:[14021363729] Sgx Registration Protocol Shall introduce user controlled read-only mode. [IPU2024.3][HSD]:[16023026057] ICX fix Hackathon Issue in UpdateVlsVariable. [IPU2024.3][HSD]:[15014975601] Fix Hackathon Issue in UpdateMirrorFailoverVariable. [IPU2024.3][HSD]:[18034465998] Fix support for SMM in IIO API library. [IPU2024.3][HSD]:[14021145725] Revert "ICX fix Hackathon Issue in UpdateMirrorFailoverVariable". [IPU2024.3][HSD]:[14021238862] Fix for Renesas SPD WA DIMM present. [IPU2024.3][HSD]:[15014975601] ICX fix Hackathon Issue in UpdateMirrorFailoverVariable. [IPU2024.3][HSD]:[14021117320] Memory latency abnormal because BIOS doesn't report correct NUMA status. [IPU2024.3][HSD]:[14021065827] AMT memtest type 18 not able to detect bad row but can be detected by memtest type 13. [IPU2024.3][HSD]:[14021070870] Advanced MemTest Test Type 20 for DDR4. [IPU2024.3][HSD]:[14021020464] MRC still communicates with PMEM even if the PMEM is disabled during late config. [IPU2024.3][HSD]:[14021033629] ADDDC Uncorrectable Spare Error is logged incorrectly. [IPU2024.3][HSD]:[14020949231] Save/Restore Software SMI during TXT. [IPU2024.3][HSD]:[22018900142] Implement the NVRAM Variable checking scripts. [IPU2024.3][HSD]:[22018932124] Revert "[ICX]Sgx Registration Protocol Shall introduce user controlled read-only mode". [IPU2024.3][HSD]:[22018932124] Sgx Registration Protocol Shall introduce user controlled read-only mode. [IPU2024.3][HSD]:[14020092349] 'Smarttest key' string unable to found in boot log after AMT TestType 16 implemented. [IPU2024.3][HSD]:[22018918375] Check whether OOB MSM DFX exists before initializing OOB MSM DFX BAR0, since OOB MSM DFX doesn't exist in production environment. [IPU2024.3] Update VROC to v8.5.0.1096 [IPU2024.3] Update XCC Production Microcode D0/D1/D2/HCC M1 m87_606a6_0d0003e7 [IPU2024.3] Update BIOSACM 1.3.7 and SINIT 1.3.8 [WhitleyPc] CpPcPlatPkg/CommonSetupLib: Sync IPU24.3 of Adv MemTest Options Help string to CpPcPlatPkg. [OpenSSL] Upgrade OpenSSL to 1.1.1u [CYP/TNP] For QSBR release modify R-version BIOS ID to R0010. [CYP/TNP] BIOS copyright should change to 2006-2024. Server-RC-0.4.2.0038 ================================================================================ R01010009 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0009 [DSG][WhitleyPC_IPU2023.4] update XCC production microcode 0d0003b9 BTS31 [CYP/TNP] [MiTAC]After load BMC default, user cannot access EWS/Redfish "BIOS configurations", it will pop caution “NOTE: BIOS Configuration information isn't available, please reboot your system to get it updated.” BTS32 [CYP/TNP] [MiTAC]After changed any "BIOS Configurations" setting in EWS, reset system, the BIOS settings have not been modified. Server-RC-0.4.2.002E [HSD]:[2103659330] [TNP/CYP] The option of 'correctable error threshold' help text info is incorrect in BIOS setup/BIOS setup spec/test case [HSD]:[2103659138] System will auto reset deadloop after modify “Reset PCI Rebalance Data” option to Enable and save in EWS OOB BIOS update. [IPU2023.3][HSD]:[22016022496]PcdCpuSmmRestrictedMemoryAccess set FALSE in latest RC [IPU2023.3][HSD]:[22016275813] Skip Fub2(MA14, MA15 and MA16) during BSSA RMT for BIOS with Dfx disable [IPU2023.3][HSD]:[18023192957] Run PCIe capabilities configuration over virtual root ports in NAC [IPU2023.3][HSD]:[14018120830] Adding Manufacturer ID Code [IPU2023.3][HSD]:[22016256132] SERM mode not being set on PCH Root Ports [IPU2023.3][HSD]:[22016281045] Assign UBOX BAR after OEM resource allocation [IPU2023.3][HSD]:[22016020052] MSR-0x790 becomes 0x0 after the injection attempt. [IPU2023.3][HSD]:[22016509241] AMT Test Type 17 + Test Type 15 combination lead to CPGC timeout [IPU2023.3][HSD]:[15011948839] Value of SetPoisonRecord should not be populated in the bios log after CE injected [IPU2023.3][HSD]:[16019391406] Harden SMM rendezvous before write to flash While writing flash region in SMM, the SMI handler disables flash protection (DisableBiosWriteProtect). [IPU2023.3][HSD]:[14018333040] In Intel Whitley code, when SRAR occurred, UEFI will try to get retry err log regs in CheckDDR4Error(), if failed, uefi will clear some bits and not think it is memory error, but not check the return status of CheckDDR4Error(), thus the code will run through below. [IPU2023.3][HSD]:[14018440405] Update MiscVendor ATM algo to version 3.7 [IPU2023.3][HSD]:[22014984381] Fix TOCTOU issue in release/icx_2021_intel_25d98 [IPU2023.3][HSD]:[14018718770] BIOS writes 0x790 before BIOS_DONE caused GPF when DAM is not enabled. [IPU2023.3] Update VROC to v8.0.0.4006 [IPU2023.3] Update XCC Production Microcode D0/D1/D2/HCC M1 m87_606a6_0d0003a5 [IPU2023.3] Update ME version to E5_04_04_04_500. Change RC version from 0x2C to 0x2E ================================================================================ R01010008 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0008 [BIOS Option Changed][CCB]:[3788] change default Correctable Error Threshold to 500 Advanced->Memory Configuration->Memory RAS and Performance Configuration->Correctable Error Threshold, default setting changed from 10 to 500. When online update BIOS need load BIOS default then the change can be taken effect. [HSD]:[2103658481] WhitleyPcPkg/PlatformSmiFlashLib: Set operation size to 4KB if total erase size less than 64KB [HSD]:[22016662248] M50CYP motherboard serial number corrupted and reverting to SPRO03200016 Server-RC-0.4.2.002C [BIOS Option Changed][HSD]:[15013115717] CpPcPlatPkg/CommonSetupLib: Hidden MCTP setup knob due to BMC workaround for TNP PMBUS Fan failure issue. Remove Server Management -> MCTP Bus Owner option [HSD]:[15013103326] ServerPlatformPkg/BuildScript: [DSG]Align IFWI id and Work Week time zone to local time zone. [HSD]:[15012876138] ServerPlatformPkg/OutofBandFeature: Use bit5 to inform BMC whether BIOS password has been set [HSD]:[15012065829] CpPcPlatPkg/PauseKeyHandling: [DSG]Remove PauseKey Handler before ReadyToBoot. [HSD]:[15012739591] WhitleyPcPkg/PlatformSmiFlashLib: Improve performance for updating BIOS capsule [HSD]:[15012200255] WhitleyPcPkg/GenerationSetup: Remove VTD Disable callback function [HSD]:[15013133519] ServerPlatformPkg/OutofBandFeature: ITK cap can't be flashed when enforced password support is enabled Server-RC-0.4.2.002B [BIOS Option Changed][HSD]:[15012721054] CpPcPlatPkg/CommonSetupLib: remove unused setup knob.Removed MCTP Broadcast Cycle setup knob since it is not useful. Remove Server Management->MCTP Broadcast Cycle option [CCB]:[3764][HSD]:[15012981186] WhitleyPcPkg/PfrSmiUpdateFw: Add SEL for ITK update status [HSD]:[15013050836] CpPcPlatPkg/ClearSettingLib: remove ITK or replace it with BIOS for ccs message [HSD]:[15013029194] CpPcPlatPkg/CommonSetupLib: Change "Enforced Password Support" to disable after clearing admin PWD [HSD]:[15012847931] WhitleyPcPkg/BuildScripts: Add update platform information in PFM bin. [HSD]:[15012739591] WhitleyPcPkg/CblSpecific: Remove the IPMI command 0x30 0x87 [HSD]:[15012803834] Type "exit" command at EFI Shell will still boot to EFI shell when enter EFI shell via F6 menu [HSD]:[14018122547] PcieGlobalAspm/Restricted: Hard code PCH port ASPM to L1 only and change per PCIE port optio [HSD]:[15012423221] WhitleyPcPkg/GenerationSetup: remove SATA string from SATA/PCIe M.2 Volume Management Device (CPU0 PCH). [HSD]:[2103638386] CpPcPlatPkg/Features: Update CopyRight to 2023 [HSD]:[1509925567] remove the code change for common.espi_smi failure issue [HSD]:[2201554298] [Cherry-pick] IPU23.1 ServerSecurityPkg/SgxEarlyInit: Security BIOS shall program msr 0x3a regardless of bootflow [HSD]:[16016328984] [Cherry-pick] [CVE-2022-32231] IPU23.1 ESPI SMI LOCK is not set. The purpose of this changes is to enable ESPI SMI Lock. [HSD]:[22015774648] [Cherry-pick] IPU23.1 CpRcPkg/LoadNvramData: Change uint to int to account for negative cases [HSD]:[15011562344] [Cherry-pick] IPU23.1 ServerSiliconPkg/UncoreLib: Devhide CHAs of disabled LLC on ICX-SP [HSD]:[22015539623] [Cherry-pick] IPU23.1 ServerSiliconPkg/PeiIioInitLib: Move call of IioLinkReTrain after EWL [HSD]:[14017158030] [Cherry-pick] IPU23.1 BIOS needs to program temp_halfxref to 0 [HSD]:[22015469479] [Cherry-pick] IPU23.1 CpRcPkg/BaseMemoryServicesLib/ConvenienceFunctions: IsDcpmmPresentChannel should check per DIMM DcpmmPresent field instead of per channel ddrtEnabled [HSD]:[14016209068] [Cherry-pick] CpRcPkg/Library/BaseMemoryCoreLib: [PLR3 Candidate][ICX]Inject UCE into failling DIMM, the PPR will show the wrong nibblemask and drammask [HSD]:[16015903381] [Cherry-pick] [ICXD HCC A0][MEMORY] MEMORY MATRIX SYSTEM (128GB LRDIMM)IS UNABLE TO BOOT with 2400MT/s speed [HSD]:[18021347488] [Cherry-pick] IPU22.3 ServerSiliconPkg/CrystalRidge: Subtract 1 from end address in ARS DSM's, so all functions work in the same way. [HSD]:[14016334192] [Cherry-pick] IPU22.3: ServerSiliconPkg/Mem/Library/MemCpgcIpLib/VendorContent: DDR4 Advanced Memtest Code update for SK hynix to V2.8.7 [HSD]:[15010878057] [Cherry-pick] IPU22.3 ServerRasPkg/RasMisc: [ICX][SMBUS][Lenovo]Smbus recovery failed on socket0 and succeeded on socket1 when Smbus errors occurred on different sockets [DSG][WhitleyPC_IPU2023.1]Sync VMDVROC drivers to v7.8.0.1012 [DSG][WhitleyPC_IPU2023.1]Update SPS FW to 04.04.04.301 [DSG][WhitleyPC_IPU2023.1]Update BIOSACM 1.3.6 and SINIT 1.3.7 [DSG][WhitleyPC_IPU2023.2]Update XCC Production Microcode D0/D1/D2/HCC M1 m87_606a6_0d000390 Server-RC-0.4.2.002A ================================================================================ R01010007 ================================================================================ Change BIOS ID to SE5C620.01.01.0007 [HSD]:[2103655321] WhitleyPcPkg/GenerationSetupString: Update the string of AtomicOp Egress Blocked Mask [HSD]:[2103655907] CpPcPlatPkg/CommonVariable: setup knobs default value were disabled using syscfg to check them Server-RC-0.4.2.0023 [CCB]:[3717][HSD]:[15011976683] CCB3717 Enable MCA Recovery in Whitley DSG Commercial BIOS [HSD]:[15011975987] PcdCpuSmmRestrictedMemoryAccess set FALSE in Whitley Sustaining phase [HSD]:[15011741796] Add X2APIC call back function to auto enable VT-D when it is enabled. [HSD]:[15012111145] It will logging ECC event log at OS when Enable MCA Recovery. [HSD]:[15011849958] Enhance SMBIOS Type 9 System Slot Table for endpoint device enumeration. Server-RC-0.4.2.0022 [BIOS Option Changed][CCB]:[3694][HSD]:[15011621856] WhitleyPcPkg/GenerationMemory: CCB3694: Add Enable Custom Refresh Enable and Custome Refresh Rate BIOS setup knobs. Add Advanced->Memory Configuration->Custom Refresh Enable, default is Disabled Add Advanced->Memory Configuration->Custom Refresh Rate, default is 20(need enable Custom Refresh Enable option first). [BIOS Option Changed][CCB]:[3695][HSD]:[15011623886] Expose 'Data Link Feature Exchange' in CYP/TNP BIOS SETUP Interface. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Data Link Feature Exchange, default is Enabled [CCB]:[3673][HSD]:[15011621801] WhitleyPcPkg/Restricted: Add "PCIE Fatal error mask settings" to CYP/TNP BIOS ITK interface [CCB]:[3627][HSD]:[15011621760] WhitleyPcPkg/PlatformPkg: Create new AXXTPMENC8+ parts for ROW based on Infineon 9672 to supersede current 9670 based parts [HSD]:[2103655182] WhitleyPcPkg/MemErrorLog: Inject Uncorrectable Non Fatal error to DIMM Rank 1 via WHEAHCT command, the SEL log show Rank 0 [HSD]:[2103654470] If admin password is set, flash BIOS with bin file isn't requested 'password ' parameter but flash .cap file is needed it. [HSD]:[2103652728] XmlCliCommon/Tool: Fix ParseSetup.py build error. [HSD]:[2103654492] ServerPlatformPkg/CustomizedDisplayLib: HII of Intel_M50CYP does not display option to select PD while creating VD [HSD]:[15011915010] CpPcPlatPkg/PlatformVariableHookLib: Add NVRAM corrupted check and set hob data NULL_VARIABLE_EVENT [HSD]:[22014698846] [Cherry-pick][SGX][ICX] - SGX Support - When SMX is fused off then SINIT & BIOS ACMs SVNs should contain Reset Value in SE SVN MSR. [HSD]:[15011871101] Revert "CpPcPlatPkg/aseSecuredSetVariableLib: unable to set BIOS admin password and Bios user password in OS Level of TNP" [HSD]:[15011838454] WhitleyPcPkg/GenerationSetup: When Enable Partial Mirror at OS, mirror related option need hidden in BIOS setup [HSD]:[15011765544] WhitleyPcPkg/GenerationSetup: sync RP SGX setup criteria and callback function. [HSD]:[15011588767] WhitleyPcPkg/GenerationSetup: Need remove DFX related options from BIOS and ITK [HSD]:[22014878309] CpRcPkg/CpRcPkg: Update on CLTT MRC whitepaper [HSD]:[22014923207] ServerSiliconPkg/MemFmcIpLib/MemFmcMailboxCommon: Generated [HSD]:[22015124973] Revert "ServerSiliconPkg/Mem/Library/MemDecodeLib: Block Decoder will not get mapped if DDR is mapped up to MMIOH" [HSD]:[14015886212] ServerSiliconPkg\Mem\Library\MemMcIpLib\Common\MemConfigMc.c: Remove page policy adaptive restriction. Server-RC-0.4.2.0021 ================================================================================ R01010006 ================================================================================ Change BIOS ID to SE5C620.01.01.0006 [BIOS Option change]:[CCB]:[3692][HSD-ES]:[15011178883] WhitleyPcPkg/Restricted: VMD PCIe address changed after FW update Add Advanced->PCI Configuration->Reset PCI Rebalance Data option, default is Disabled [CCB]:[3622][HSD-ES]:[15011020304] WhitleyPcPkg/Uba/UbaMain/TypeCoyotePass: CCB3622 Enable CPU1 SlimSAS ports when CYP Interposer module is connected to CPU0 [HSD-ES]:[2103653665] WhitleyPcPkg/Uba/SmbiosDataUpdateDxe: [MiTAC] After enable VMD, the NVME SSDs connected to CPU0 3x port are mapped as CPU0 PCIe 2x port in RSD Type 194 and EWS.(Regression) [HSD-ES]:[2103652088] CpPcPlatPkg/PlatformWatchdogTimerLib. Remove extra WhitleypcPkg definition [HSD-ES]:[2103652083] Revert "CpPcPlatPkg\Library\CommonSetupLib: Correct Console Redirection expression for EWS." [HSD-ES]:[2103652819] Revert "CpPcPlatPkg/Password: [DSG][pen-test] No Password Salt or System Wide Salt Used" [HSD-ES]:[2103652714] WhitleyPcPkg/GenerationSetup: Remove unnecessary option information. [HSD-ES]:[2103648335] WhitleyPcPkg/SelLogLib: PPR finish log is shown as Critical severity in EWS after inject CE to DIMM [HSD-ES]:[15011379852] WhitleyPcPkg/* : Update default code reviewer for Whitley commercial Platform [HSD-ES]:[15011558718] ServerSecurityPkg/Sgx: Revert "[SGX][ICX] - SGX Support - When SMX is fused off then SINIT & BIOS ACMs SVNs should contain Reset Value in SE SVN MSR." Server-RC-0.4.2.0020 [Hsd-ES]:[2103652088] CpPcPlatPkg/Library: SUT does FRB2 reset when system under driver health manager screen of destroyed RAID volume. [Hsd-ES]:[2103651861] CpPcPlatPkg/ITK50: System cannot save the BIOS setting after load BIOS default by syscfg or sysfwupdt utility [Hsd-ES]:[15011215869] CpPcPlatPkg/Password: [DSG][pen-test] No Password Salt or System Wide Salt Used [Hsd-ES]:[22103651902] WhitleyPcPkg/SmbiosDataUpdateDxe: "Connector type" is wrong for M.2 NVMe SSD under EWS-->Storage information [Hsd-ES]:[15011209414] WhitleyPcPkg/SetupLib: [PTK0002709]Intel Server BIOS Buffer overflow vulnerability. [Hsd-ES]:[15011347802] WhitleyPcPkg/FlashUpdateLib: ME version is incorrect in BMC Event Log Server-RC-0.4.2.001F [BIOS Option change]:[CCB]:[3584][Hsd-ES]:[15010770843] WhitleyPcPkg/SmbiosDataUpdateDxe: CCB 3584 [BIOS] Redfish NIC config Knobs and SMBIOS type 42 for Redfish (Clone Purley CCB3158) Add Server Management->BMC LAN Configuration->"HI BMC Lan Configuration/HI Host LAN configuration" related settings [CCB]:[3622][Hsd-ES]:[15011020304] WhitleyPcPkg/Uba/TypeCoyotePass: CCB3622 Enable CPU1 SlimSAS ports when CYP Interposer module is connected to CPU0. [CCB]:[3473][Hsd-ES]:[15010873024] CpPcPlatPkg/SecureBootErrorHandler: [CCB3473]Log SEL when OptionROM fails to verify with UEFI secure boot. Do not hang system boot or wait for key. [CCB]:[3609][Hsd-ES]:[15010770752] WhitleyPcPkg/ClearFRB2TimeoutCounter: CCB 3609 [BMC/BIOS] Improve FRB2 behavior so on 3 attempt it is disabled [CCB]:[3535][Hsd-ES]:[15010770685] WhitleyPcPkg/Restricted: Change 'RAPL limit MSR Lock' knob value into Enable. [CCB]:[3610][Hsd-ES]:[15010770813] ServerSecurityPkg/Pfr: Improve Pfr panic checkpoint [Hsd-ES]:[2103644614] CpPcPlatPkg\Library\CommonSetupLib: Correct Console Redirection expression for EWS. [Hsd-ES]:[2103650268] WhitleyPcPkg\Restricted\Platform\Dxe\GenerationSetup,Correct callback issue. [Hsd-ES]:[2103644020] WhitleyPcPkg/Setup: Correct SOL for Baseboard Mgmt2 option handling on CYP. [Hsd-ES]:[15010590176] WhitleyPcPkg/SystemDiagnosticDxe: Remove AMT complete SEL [Hsd-ES]:[15011182852] WhitleyPcPkg/PlatformSetupVariableSyncLib: Enable PCIe ATS on Whitley BIOS [Hsd-ES]:[15011206608] CpRcPkg: Update RC version to 001B to align RP PLR3 Beta Candidate RC version 001C. [Hsd-ES]:[14016342444] WhitleyPcPkg/EwlParseLib: M50CYP SUP R0005 does not report bad DIMM in POST message. [Hsd-ES]:[22014887190] Change PFR Watchdog Timer behavior to meet product requirements Problem. [Hsd-ES]:[15011062024] CpPcPlatPkg/Restricted: Change the GenITK tool from GenITK.exe into GenITK.py [Hsd-ES]:[15011040227] ServerPlatPkg/SetupBmcCfg: SUT can't log in the EWS when a user with a 20 characters password created in the BIOS setup [Hsd-ES]:[15010775402] CpPcPlatPkg/ITK50: ITK setting still can be applied successfully when PFR flash active BIOS failed. [Hsd-ES]:[16015331172] WhitleyPcPkg/PlatformSetupVariableSyncLib: SATA and sSATA Driver depex [Hsd-ES]:[15011197631] WhitleyPcPkg/DxeSetupLib: PTK0002709: Intel Server BIOS Buffer overflow vulnerability [Hsd-ES]:[2014627819] [Cherry-pick]SouthClusterLbg/SPI Fixed SPI PCIe config base after changing to 3G base [Hsd-ES]:[18019438530] [Cherry-pick]ServerSiliconPkg/Iio: Clear ITCCTRL23.rcb128 to align MS3IOSF RCB to PCIe RCB [Hsd-ES]:[15010809178] [Cherry-pick]ServerRasPkg/RasMisc: [Lenovo][Whitley] BMC received incorrect DIMM temperature data when DIMM SMBus met recovery situation (due to BIOS disabling the CLTT) [Hsd-ES]:[22014638487] [Cherry-pick]CpRcPkg/BaseMemoryCoreLib: RemoveInvalidPprEntry input parameter is Ch in Socket (0 to 7) and PprAddrSetup uses mc Channel (0 to 1)"" [Hsd-ES]:[22014623287] [Cherry-pick]ServerSiliconPkg/Mem: ICX Media Disabled Pmem module preventing reprovisioning of other modules on socket [Hsd-ES]:[22014700950] [Cherry-pick]ServerSiliconPkg/MemoryEvContent: BSSA RMT fix for per bit margins [Hsd-ES]:[22014671673] [Cherry-pick]ServerPlatformPkg/Platform: [IDVL_LCC_FW_EVAL]Copyright tag shows old value in BIOS page. [Hsd-ES]:[22014638461] [Cherry-pick]ServerSiliconPkg/Mem/Library/MemDecodeLib: Block Decoder will not get mapped if DDR is mapped up to MMIOH [Hsd-ES]:[22014631175] [Cherry-pick]ServerSiliconPkg\Library\MemPwrTempTableLib\Wave1\MemWeightTable.c: Adding settings for DDR_2666 [Hsd-ES]:[22014638962] [Cherry-pick]ServerSiliconPkg: Remove HMRC WA from IPClean BIOS source [Hsd-ES]:[22014638861] [Cherry-pick]ServerSiliconPkg/MemMapDataLib: The Memory RAS code may clean and corrupt the SystemMemoryMap structure if the VariableSize being hacked to a large value [Hsd-ES]:[22014638800] [Cherry-pick]ServerSiliconPkg/Iio: [PCI] Updating help text for Relaxed Ordering option. [Hsd-ES]:[22014630286] [Cherry-pick]ServerSiliconPkg/Mem: Silent Data Corruption occurs when Reversing and Forward ADDDC Rank Sparing [Hsd-ES]:[22014637898] [Cherry-pick]ServerSiliconPkg/MemCpgcIpLib: Fix cpgcGblTrainingSetup.rwMode overwritten to read mode [Hsd-ES]:[18018607038] [Cherry-pick]ServerSiliconPkg/CrystalRidge: ServerSiliconPkg/JedecNvdimm: Change the way which buffer is passed between DXE and SMM drivers from UEFI variable to protocols [Hsd-ES]:[22014637927] [Cherry-pick]CpRcPkg/BaseMemoryCoreLib: EWL logging is missing for UCE PPR using failing DIMM [Hsd-ES]:[22014637905] [Cherry-pick]CpRcPkg/Library/BaseMemoryCoreLib, ServerSiliconPkg/Library/ProcMemInit: Program Margin Read to reduced or increased values in case TSE EEPROM CRC failures [Hsd-ES]:[22014638380] [Cherry-pick]ServerRasPkg/Library: when eMCA enabled MCE is not propagated to socket1 after socket0-punit catastrophic error injection [Hsd-ES]:[22014638893] [Cherry-pick][Whitley] Inclusion of SGX NVRAM manifest file in firmware build [Hsd-ES]:[14015874261] [Cherry-pick]Intel\ServerPlatformPkg:BaseResetSystemLinConstructor() is launched prior [Hsd-ES]:[22014698846] [Cherry-pick][SGX][ICX] - SGX Support - When SMX is fused off then SINIT & BIOS ACMs SVNs should contain Reset Value in SE SVN MSR. [Hsd-ES]:[15010270944] [Cherry-pick]ServerRasPkg/Driver/Smm/PprVlsErrorLogListener: Memory ce skip ppr [Inclusive language]CpPcPlatPkg/Features: Replace deprecated terms in source code and remove some end of line space and tab. CpPcPlatPkg/OemPostScreenDisplayDxe: Change copyright of OEM post screen. Update IioBifurInit.c Server-RC-0.4.2.001C ================================================================================ R01.01.0005 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0005 [CCB]:[3446] [BIOS]ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) below two case will allow to update itk cap. 1. ITK biosid matched with currently biosid 2. ITK biosid isn't matched with currently biosid, but matched with pch stage biosid. [Hsd-ES]:[15010599213] [Whitley][BIOS] ITK resolution issue : Update ITK BIOS, reset system, and then System hang up at black screen after pressing F2/F6 Improve FRB- function ServerPlatformPkg/GenericIpmi: keep Getdeviceid () retries to 120s Update SVN version.change SVN version to 2 to not allow downgrade BIOS due to securtiy issue. Enable PFR settings.for static region, enable RecoverDurings to 1, for BIOS dynamic region, only enable RecoverDuring3. [Hsd-ES]:[2103646731] [MiTAC] The BIOS is not updated and there isn't SEL for the change after update ITK capsule with OOB method. [Hsd-ES]:[2103646245] [MiTAC] System can't prompt 'Fatal Error : System Encounter A Stopper Error' after disable 'promote Warnings' option. [Hsd-ES]:[2103646616] [MiTAC] The POST Err Sensor is wrong parsed as 'Event type 6f, offset 4' after system reboot [Hsd-ES]:[2103647675] [MiTAC] After set the mirrored memory 20% mirrored above 4GB, current configuration is still shown as 'unknown' even change mirror mode to full mirror. [Hsd-ES]:[2103647670] [MiTAC] After set the mirrored memory 20% mirrored above 4GB, there is unexpected message in SEL log and '85fc' error code occurs in error manager. [Hsd-ES]:[2103647720] [Whitley][CYP]BCM NIC FW not show in BMC Web NIC information page. [Hsd-ES]:[15010432715] [Whitley][BIOS] IPS00657497- Boot Failure with Adaptec Raid 3254/3258 on CYP Riser2 Slot1 [Hsd-ES]:[15010209598] [21'Q4 CCB3462]BIOS administrator password will not be bypassed when FORCE_EFI_BOOT or FORCE_EFI_BOOT_SILENT is detected. [Hsd-ES]:[15010412593] The bifurcation setting value of M20464 riser card isn’t mapped with PCIE port info. [Hsd-ES]:[15010158887] Add suppor for Adaptec 3200 card. [Hsd-ES]:[15010031315] Correct the Comments message. [Hsd-ES]:[15010008515] If (RRL dev ==0) skip try Bank/Rank vls for the buddy bank/rank. [Hsd-ES]:[14015742100] Update on starve settings for VC0 deadlock. breaker for DDR4 scheduler deadlock bug [Hsd-ES]:[1509970724] Skip rankvls promotion when bankvls in single rank. Change copy right to 2022 Fix debug bios assert issue after clear cmos Change build output path into dynamic mode. Fix release path issue.Remove EGS part. Server-RC-0.4.2.0012 [BIOS Option change] [Hsd-ES]:[2103646733] [MiTAC] The current configuration will show as 'Unknown' after enable Mirror TAD0 and UEFI ARM Mirror Remove “UEFI ARM Mirror” at BIOS setup Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Removed [BIOS Option change] [Hsd-ES]:[2103646654] [MiTAC] After flashed 0027P07 BIOS and reboot, there is critical error log in EWS for SPS FW Health and STATUS_LED blinking with orange. Service Managerment->MCTP Bus Owner->Value range"0-65535", "520" is default setting; [Hsd-ES]:[1509988050] Setup and Help Items do not match SPEC and wrong spelling [Hsd-ES]:[2103646622] [MiTAC] The POST Err Sensor according ED value is shown as 0000 after system reboot [Hsd-ES]:[15010168104] [21'Q4 CCB3431] partial mirror mode can't be set successfully [Hsd-ES]:[2103646697] [MiTAC] There isn't EWS log after change mirror mode value to dsiable or partial Mirror Mode. [Hsd-ES]:[2103646659] [MiTAC] After inject CE to memory, there is only one Post Package Repair finish log. [Hsd-ES]:[2103646729] [MiTAC] System always reset during POST after enable SGX and disable TME [Hsd-ES]:[2103646886] [MiTAC] Only 19 PPR request logs are generated even inject over 21 times CE error to dimm no matter PPR type is Hard or Soft PPR. [Hsd-ES]:[2103646639] [MiTAC] System can't power up after downgrade BIOS from 0027P07 to R01010004 through OOB. [Hsd-ES]:[2103646782] [MiTAC] There is no SEL log and RED warning message shown on POST screen after flash a second mismatched ITK capsule. [Hsd-ES]:[22013752711] [Cherry-pick]ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. [Hsd-ES]:[16015331172] There is no VROC option ROM after enable VMD [Hsd-ES]:[2103646736] [MiTAC] System will always show a message after Enable ARM Mirror and set a value for ARM Mirror percentage. [Hsd-ES]:[2103646941] [MiTAC] With PPR type is Hard or Soft PPR setting, no PPR finished logs indicate correct memory slot/Rank after inject UCE error and has more unknown extra logs appear. [Hsd-ES]:[15010209598] [21'Q4 CCB3462]BIOS administrator password will not be bypassed when FORCE_EFI_BOOT or FORCE_EFI_BOOT_SILENT is detected. [Hsd-ES]:[2103647317] [MiTAC] Some items can be changed&saved when enter BIOS setup with user password. [Hsd-ES]:[2103646245] [MiTAC] System can't prompt 'Fatal Error : System Encounter A Stopper Error' after disable 'promote Warnings' option. add a tool for generate BIOS flash layout information. Update on starve settings for VC0 deadlock breaker for DDR4 scheduler deadlock bug" Fix Oob capsule generation failure. Due to completion timeout accessing main memory with RDIMM and PMEM in memory mode. 1) Adding PcdStarveTimer and PcdStarveThreshold with default values 0x12 and 0x4. 2) Adding PcdKeepStarveSettings to control if customer wants to keep BIOS settings(default should be TRUE) or let Pcode change the settings(FALSE) to new default settings(0x12 and 4). [Whitley][ICX][PLR1 Beta] system hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" Correct the calculation under partial mirror by size Server-RC-0.4.2.0010 [BIOS Option change] [Hsd-ES]:[1509848893] Remove “callback” for User Privilege at BIOS setup. Server Management->BMC LAN Configuration->User Configuration->Privilege->User/Operator/Administrator/No Access, No Access is default setting;(Remove "Callback") [BIOS Option change] [Hsd-ES]:[1509837959] Change "Uncore Freq" option range be 8 to 22 Advanced->Power & Performance->Uncore Power Management->Uncore Freq->Value range"8-22", "22" is default setting;(Uncore Freq Scaling need to set to disable before change Uncore Freq value) [BIOS Option change] [CCB]:[3504] [Hsd-ES]:[1509979164] CCB 3504 Enable OS Native AER SupporMenut in BIOS Setup Advanced->System Event Log->OS Native AER Support->Disabled/Enabled, Disabled is default setting; [BIOS Option change] [CCB]:[3431] [Hsd-ES]:[1509866088] CCB3431 [Whitley][BIOS]Support Address range/partial memory mirroring feature on CYP/TNP BIOS Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Disabled/Full Mirror Mode/Partial Mirror Mode, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror TAD0->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Partial Mirror Mode->Partial Mirror X Size(GB)->"0" is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Enable->ARM Mirror percentage->"0" is default setting; [BIOS Option change] [CCB]:[3428] [Hsd-ES]:[1509980595] CCB3428 [Whitley][BIOS] Expose PPR knob to commercial CYP/TNP BIOS (Sync up Purley CCB3027 to Whitley) Advanced->Memory Configuration->PPR Type->Hard PPR/Soft PPR/PPR Disabled, Hard PPR is default setting; [BIOS Option change] [CCB]:[3429] [Hsd-ES]:[1509980529] CCB3429 [BIOS-Align Purley] Enable Advanced MemTest for CYP/TNP BIOS(Sync up Purley CCB3178 to Whitley) Advanced->Memory Configuration->MemTest->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->MemTest Loops->"1" is default setting; Advanced->Memory Configuration->Adv MemTest Options->"0" is default setting; Advanced->Memory Configuration->Adv MemTest PPR Flow->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Retry After Repair->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Reset Failure Tracking List->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Adv MemTest Conditions->Disabled/Auto/Manual, Auto is default setting; [BIOS Option change] Remove "L1 only" option for PCIe ASPM Support (Global) option. Advanced->Integrated IO Configuration->PCIe Misc. Configuration->PCIe ASPM Support(Global)->Per invididual port/Disabled, Per individual port is default setting; [Hsd-ES]:[1509979099] [CCB]:[3443] CCB 3443 [Whitley Q3'21 BMC/BIOS] Port InSyde new features to Whitely BMC & BIOS Service Managerment->MCTP Bus Owner->Value range"0-9999", "0" is default setting; Service Managerment->MCTP Broadcast Cycle->Disabled/Enabled, Disabled is default setting; [Hsd-ES]:[1509980437] [CCB]:[3462]CCB3462 [BIOS & BMC]Bypass BIOS admin password when FORCE_EFI_BOOT or SILENT_FORCE_EFI_BOOT is detected [Hsd-ES]:[2103643900] [CCB]:[3524][CCB3524][MiTAC] Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[1509979269] [CCB]:[3422] CCB 3422 [Whitley][BIOS/BMC] Sync up Purley RAS SEL log code to Whitley(Purley CCB 3245/3386/3388/3389 ) [Hsd-ES]:[1509979025] [CCB]:[3423]CCB 3423 [BIOS-Align Purley] Request PPR within SW Error Threshold Flow for new row entries [Hsd-ES]:[1509979201] [CCB]:[3446]CCB 3446 [BIOS]ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) [Hsd-ES]:[1509955510] Remove unused variables in PC_GENERATION_VOLATILE structure. [Hsd-ES]:[2103643984] Hide 'SOL for Baseboard Mgmt2' option on TNP. [Hsd-ES]:[1509988050] Setup and Help Items do not match SPEC and wrong spelling [Hsd-ES]:[1509925567] [21'Q4]espi_smi failed in the log while run "chipsec_main -vv" in windows2022 with chipsec tool 1.7.1(New Tool) [Hsd-ES]:[1508596630] Add reserved variable for RP [Hsd-ES]:[14015052253] use AllocatePages to save SysSetup/EmulationSetting/CpuAndRevision into memory [Hsd-ES]:[22013740541] [BIOS] NXM Hole Range reported as Reserved with PRMRR setting 256GB with system memory populated with 768GB [Hsd-ES]:[22013771171] [ICX] 3R2W interleave implementation has code dependency on DFX knob PcdBiosDfxKnobEnabled [Hsd-ES]:[1509723062] SMBIOS Mux Pin Handling and CPLD/Retimer FW update design enhancement . [Hsd-ES]:[18018321208] Enable si w/a 22013005570 [Hsd-ES]:[22013866480] [ICX Whitley][CPU 6330] BIOS hangs when MMCFG value is set to values as 1.5G and NUMA sets disabled. [Hsd-ES]:[22013803749] Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[22013801355] Clear CAP errors at boot in MC banks [Hsd-ES]:[15010169018] Add '_SM' in to IFWI name. [Hsd-ES]:[15010100174] Add buffer boundary check [Hsd-ES]:[1509882567] clear SNC registers in no-memory config [Hsd-ES]:[22013035870] System occurred iMC data parity error with MCACOD = 405 during stress [Hsd-ES]:[14015513993] [Whitley][ICX][PLR1 Beta] system hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" [Hsd-ES]:[15010129062] Fix compiler warning [Hsd-ES]:[18019090175] Fixed detection MROM1 based on softstrap configuration Change BIOS ID to SE5C6200.86B.0027.P07 Switch to new branch [wlypc_qsbr_rel] (release/wlypc_2021_intel_23d50) Lock SMBIOS Mux Reset GPIO Pin TX State. Sync AMP code with CYP and TNP ================================================================================ R01.01.0004 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0004 Update XCC D0/D1/D2 & HCC M1 microcode to 0x0d000311 [Hsd-ES]:[2103644190] [Cherry-pick]WhitleyPcPkg/Network.dsc.inc: Set NETWORK_ISCSI_ENABLE to TRUE for supporting iSCSI [Hsd-ES]:[2103643272] "Resume On AC Power Loss" without roll back to ITK_Default value when clear CMOS. [Hsd-ES]:[1509848970] Intel(R) Virtualization Technology always disabled after command load default. [Hsd-ES]:[2103643269] Correct Riser1 retimer M20464-100 slot bifurcation function. [Hsd-ES]:[1509863439] ServerPlatformPkg/PlatformBootManagerLib: TPM firmware can't be updated successfully. [Hsd-ES]:[22013752711] [Cherry-pick]ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. Server-RC-0.2.2.003a [BIOS Option change][Hsd-ES]:[1509744702] Set promote warning default to disable Advanced->Memory Configuration->Promote Warnings->Disabled/Enabled, Disabled is default setting; [BIOS Option change][Hsd-ES]:[22013088992], Public BIOS Setup Documentation does not include description of Syscfg accessible feature "Snooped Response Wait Time for Posted Prefetch" Advanced->Integration IO Configuration->Snoop Response Hold Off->Value range"0-0xf", "9" is default setting; [CCB]:[3393] Excludes SG1 Video as VGA device [Hsd-ES]:[1509687799] removing unsupported BIOS options from SETUP/ITK interface [Hsd-ES]:[2103635229] Add PTU key to DB [Hsd-ES]:[1509758508] Correct the help text pf Processor PCIe Link Speed [Hsd-ES]:[1509733004] Fix the ADDDC rank is wrong [Hsd-ES]:[2103643023] [MiTAC] Core Count of SMBIOS type 4 will be changed after change active processor cores. [Hsd-ES]:[2103641737] Update 1U_2Slot_Riser2_SlimSAS_Interpose slot number. Support Python36 build. Fix build errors for updating Edk2 repo merge latest American Pass code change based on 20P34 [Hsd-ES]:[18016159697] Update Mgphy Recipe 3.8 to add ATernate Attentuator Table set values Add depex for VMD driver This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.34 Server-RC-0.2.2.0037 [BIOS Option change][CCB]:[3343][Hsd-ES]:[1509325487], CCB 3343 Add option to turn ON/OFF->SET Uncore Frequency Scaling Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling->Disabled/Enabled, Enabled is default setting; Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling(Disabled)->Uncore Freq->Value range "8-22", "22" is default setting; [BIOS Option change][CCB]:[3438][Hsd-ES]:[1509325384], CCB 3438 [Whitley Q3'21][BIOS]Expose RP AVX knobs to CYP/TNP BIOS Advanced->Power & Performance->CPU P State Control->AVX Licence Pre-Grant Override->Disable/Enabled, Disabled is default setting; [CCB]：[3430][Hsd-ES]:[1509325686][Whitley Q3'21][BIOS/BMC-Align Purley] Modify BIOS setup behavior around complex password(Sync up Purley CCB3356 to Whitley) [Hsd-ES]:[2103639726] Correct method to fetch VideoExist variable. [Hsd-ES]:[1509423750] system will hang EE after running CST. [Hsd-ES]:[1509331555] Add Usb keyboard/mouse detected information in Diagnostic Screen This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.32 Server-RC-0.2.2.0036 [CCB]:[3433][Hsd-ES]:[1509325431] [Whitley Q3'21][BIOS-Align Purley]Check for #FORCE_EFI_BOOT_SILENT marker file in startup.nsh [CCB]:[3359][Hsd-ES]:[16012329091] 'Vendor' part is not getting updated using ITK Tool(CCB 3359). [Hsd-ES]:[2103640684] [6 SW CCB] The behavior is incorrect after NVRAM corruption. [Hsd-ES]:[2103639726] Add COMMON VOLATILE variable VideoExist. [Hsd-ES]:[2103641115] [MiTAC] Bios option of "VMD for Direct Assign (CPU0, IOU1)" show on RISER1 VMD page is incorrect. [Hsd-ES]:[1509242103] Sync PfrShellCommands driver from WhitelyRpPkg [Hsd-ES]:[2103635892] Correct RSD SMBIOS Type 190 data. [Hsd-ES]:[2103639312] Correct Type 194 data. [Hsd-ES]:[1509334369] [CCB_3421]Modification of ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect, flash the modified ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect. [Hsd-ES]:[2103639009] Integrate American Pass BIOS changes This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.31 Server-RC-0.2.2.0035 [Hsd-ES]:[1509283474] VT-d / VT / TXT value cannot be changed via ITK [Hsd-ES]:[1508772959] Fix that DCM console display storage capacity is 0 in inventory information and health status is unknown [Hsd-ES]:[1508841934] No error info feedback when flash corrupted image with sysfwupdt(14.2 build9) [Hsd-ES]:[1509267104] Correct OCP port slot number. [Hsd-ES]:[2103639620] Correct slot number per riser accordingly. [Hsd-ES]:[2103639625] [MiTAC][ICX]SMBIOS type 9, 192 and 200 are incorrect with retimer(PBA K81522-101) attached.(Q3QSBR) [Hsd-ES]:[2103640322] [MiTAC] Stop Bits is 0 on ACPI SPCR table. [Hsd-ES]:[14014136819] Incorrect pointer caused while loop hang. This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.30 Server-RC-0.2.2.0034 [BIOS Option change][CCB]:[3421][Hsd-ES]:[1509075812]Gen3 Ph3 TxEq Manual Precursor/ Postcursor default value change. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->UniPhy/Manual, UniPhy is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->MgPhy/Manual Ph3, MgPhy is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->Ph3 TxEq Precursor->Value range"0-63", "9" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->Ph3 TxEq Postcursor->Value range"0-63", "4" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->Ph3 TxEq Precursor->Value range"0-63", "0" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->Ph3 TxEq Postcursor->Value range"0-63", "13" is default setting; [BIOS Option change][CCB]:[3407][Hsd-ES]:[14013786502], VMD Direct Assign Not Implemented in the Coyote Pass BIOS Advanced->Integration IO Configuration->Volume Management Device->XXX Volume Management Device(CPUX XXX)->VMD for Direct Assign(XXX)->Disabled/Enabled, Disabled is default setting; [BIOS Option change][CCB]:[3340]Patch3:Implement Per Port ASPM setting feature. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->PCIe ASPM Support->Disabled/L1 Only, "L1 Only" is default setting; [BIOS Option change][CCB]:[3367][Hsd-ES]:[1509035691][CCB3367] Add bank threshold function. Advanced->Memory Configuration->Memory RAS and Performance Configuration->Triger SW Error Threshold->Enabled/Disabled, Enabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->SW Per Bank Threshold->Value range "1-0x7FFF", "4" is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->SW Correctable Error Time Window->Value range "0-24", "24" is default setting; [BIOS Option change][CCB]:[3366][Hsd-ES]:[16012325043], [CCB3366]Request to add per-port knob for ECRC configuration in BIOS menu. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->ECRC Generation->Disabled/Enabled, Disabled is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->ECRC Check->Disabled/Enabled, Disabled is default setting; [BIOS Option change][CCB]:[3346][Hsd-ES]:[1509035633], Part of CCB 3346 Support secure-core in BIOS Advanced->Integration IO Configuration->Pre-boot DMA Protection->Enabled/Disabled, Disabled is default setting;(Change this option need set Intel(R) VT for Directed I/O to Enable first) [Hsd-ES]:[1509243170], DMA Control Opt-in Flag and Pre-boot DMA Protection should be hidden when VT-D set to disable [Hsd-ES]:[2103639614], SFUP FW update will not record BIOS update information event [Hsd-ES]:[1509019075], Sync WhitleyPcPkg with WhitleyRpPkg code [Hsd-ES]:[1509206537], CCB 3340 Root port help string not match the option name [Hsd-ES]:[2103640145], In BMC force update mode,BIOS/ME inband update fail with sysfwupdt tool. [Hsd-ES]:[2103640245], Patch 2 .Gray out setup Sub NUMA item if CPU core numbers is less than 12. [Hsd-ES]:[2103640169], ITK BIOS option doesn't match "intel tool support list" form Spec_v1.02_Premark03252021. [Hsd-ES]:[1509185597], Whitley KW issue reported when merging AMP code. [Hsd-ES]:[1509173438], Correct PCIe ASPM Support option setting. [Hsd-ES]:[1509173445], CCB 3366/CCB3340:Use the ITK tool to change the values of the ECRC and ASPM options under each root port under the BIOS Advanced > Inegrated IO Configuration > PCIe Misc.Configuration interface, [Hsd-ES]:[16013309544], set_biosconfig command failed and with "ProcessorHyperThreadingDisable" option [Hsd-ES]:[22011580137], SDP:Increase the size of core in CPU Socket Configuration for Coyote Pass [Hsd-ES]:[2103639777], BIOS Version contain build time on Setup Main screen with custom BIOS revision. [Hsd-ES]:[14013449243], Whitley UEFI Firmware Flash Update Library Local Auto-Variable Address Assigned to Function Parameter [Hsd-ES]:[1509105820], Correct System event log help text as View/Configure system event log information and settings. [Hsd-ES]:[1509046234], Correct SGX comments align with RP bios [Hsd-ES]:[2103639570], Correct Processer UPI Error programming. merge AMP code into Whitley trunk This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.29 Server-RC-0.2.2.0033 ================================================================================ R01.01.0003 ================================================================================ 1. Change BIOS ID to SE5C620.86B.01.01.0003 2. Merge code change to fix 2103639051 [MiTAC][ICX][CCB 3327]SUT will not auto power on at second T-1 state after flash BIOS recovery region via Sysfwupdt_V14_2_Build9. ================================================================================ R01.01.0002 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0002