================================================================================ DATE : February 3, 2023 TO : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers SUBJECT : BIOS Release notes ================================================================================ LEGAL INFORMATION ================================================================================ Information in this document is provided in connection with Intel Products and for the purpose of supporting Intel developed server boards and systems. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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Copyright (C) 2023 Intel Corporation. ================================================================================ ABOUT THIS RELEASE ================================================================================ Build Stamp: SE5C620.86B.01.02.0007.2301300850 Build Date: January 30, 2023 ================================================================================ Supported Platforms ================================================================================ D40AMP Family R01020007_AmericanPass_LBG_ICX_UpdateCapsule_prd.bin Checksum: 0x5AE63DF4 SFID offset: 0x7B8024 SFID value: 0x672AD71F ================================================================================ BIOS COMPONENTS/CONTENTS ================================================================================ Processors supported: Intel(R) Xeon(R) Scalable Processors 3rd Generation Microcode versions: CPUID Version Status 606a4 0x0b000280 (ICX-SP HCC L0) 606a5 0x0c0002f0 (ICX-SP XCC C0) 606a6 0x0d00037b (ICX-SP XCC D0/D1/D2 & HCC M1) SATAAHCI: v2.00i VROCSataEfi: v7.8.0.1012 VROCsSataEfi: v7.8.0.1012 BIOSACM: Production,v1.1.0_20211117_LBG SINIT: Production,v1.1.0_20211117_LBG NvmDimmDriver: v02.00.00.3886 NvmDimmHii: v02.00.00.3886 ASTVBIOS: v1.09 VMDVROC2: v7.8.0.1012 VMDVROC1: v7.8.0.1012 SPS: 04.04.04.202 PCH PFR SVN: 02 ================================================================================ INSTALLATION NOTES ================================================================================ WARNING: It is very important to follow these instructions as they are written. Failure to update using the proper procedure may cause damage to your system. Firmware Update Tools: Sysfwupdt 1. Copy the entire contents of the SUP package to a USB flash drive. All of the files from the package must reside in the same directory. 2. Boot to the UEFI Shell and make the mapped USB Flash device the default drive. Example: Shell> fs0: (or fs1:) 3. Run UpdBIOS_AMP.nsh script 4. The system will reboot automatically after BIOS update is complete. The screen will be blank for several minutes and the system status LED will blink green/yellow while the ID LED will stay on. 5. Do *NOT* interrupt this process. 6. After update is fully done, the system will power on automatically ================================================================================ SVN_BYPASS Jumper ================================================================================ The BIOS SVN Downgrade Jumper is labeled SVN_BYPASS on the server board. When this jumper is moved from its default position (pins 1–2), it allows the module firmware (including BIOS) in the PFR-controlled PCH capsule file to be downgraded to a lower Security Version Number (SVN). This jumper is used when there is a need for the compute module to power on using a BIOS revision with a lower SVN. To use the SVN Bypass jumper, perform the following steps: 1. Power down the selected compute module. 2. Remove the compute module from the chassis 3. Remove the riser assembly #2 from the compute module. 4. Move the “SVN_Bypass” (J16) jumper from pins 1–2 (Default) to pins 2–3 (Enabled). 5. Reinstall the compute module in the chassis. 6. Power on the compute module. The system automatically boots to the EFI shell. 7. Update the BIOS by running the command: sysfwupdt.efi -u xxx.bin -recovery. 8. After the BIOS update has successfully completed, power down the compute module. 9. Remove the compute module from the chassis. 10. Move the “SVN_Bypass” (J16) jumper back to pins 1–2 (default). 11. Reinstall the riser assembly #2 into the compute module. 11. Reinstall the compute module in the chassis. 12. Power on the compute module. During POST, press to access the BIOS Setup utility to configure and save desired BIOS options. ================================================================================ IMPORTANT NOTES ================================================================================ 1. Please use flash programmer to update BIOS to version 1019.D39. 2. Please add parameter "UpdateNvram" during online upgrade to the BIOS A019D39. 3. Please add parameter "UpdateNvram" during online upgrade to the BIOS A020P17. Update BIOS with the command: sysfwupdt.efi -u XXX_UpdateCapsule.bin UpdateNvram (Please use Sysfwupdt_V14_2_Build3 or newer versions) Note: Customer's settings will be lost after update with "UpdateNvram" parameter 4. Starting form the version 20P19, BIOS release package contains flash update utility Sysfwupdt_V14_2_Build9 which works with BIOS 20P15 or later. If the system BIOS is lower than 20P15, please update the BIOS to the version 20P15 first and after that update to the latest BIOS. 5. BIOS 20P19 and flash tool Sysfwupdt_V14_2_Build9 require BMC 2.72 or later, otherwise system will not auto power on after flashing BIOS. Please refer to the issue 2103638640 for details. 6. BIOS 20P19 and flash tool Sysfwupdt_V14_2_Build9 have below known issues: 2103638642/2103638732/2103639051. 7. Starting from A020.P17, AMP PFR Provision default has changed to "Enable". 8. Starting from A020.P23, AMP modified SPS setting of DCI Enable = 0. 9. BIOS A020.P25 require the correct BMC and CPLD, otherwise customers may face known issues: 2103638642/2103638732/2103639051/2103639969. Please refer to the ReleaseNotes_R01010003_ICX.txt for details. 10. When flashing the BIOS image which has the SVN lower than the currently installed verion, need to add "-recovery" parameter to the flash command. (e.g. sysfwupdt.efi -u xxx.bin -recovery) 11. Starting form the version B020.P30, PFR Lock default state has changed to "Enable" to follow TNP/CYP. 12. Starting from the version B020.P30, HW Validation Test Only page in BIOS setup utility is hidden following TNP/CYP. 13. BIOS R01.02.0007 includes many code changes compared to previous versions. Please add "UpdateNvram" parameter to the update command. 14. Starting from BIOS R01.02.0007 the PCH SVN has been updated to 02. The update command requires the "-recovery" parameter when updating from BIOS which has lower SVN. (e.g. sysfwupdt.efi -u xxx.bin -recovery) ================================================================================ KNOWN ISSUES/WORKAROUND ================================================================================ 1.Starting from B020.P24, BIOS by default reads GPIO pin to detect which backplane is installed in system. For AMP alpha motherboard and U.2 backplane without reworked GPIO, BIOS will not recognize backplane and will not enable VPP hotplug for IIO PCIe port. W/A: In BIOS Setup navigate to Advanced -> HW Validation Test Only page, enable "BP Auto Detect WorkAround". This will force BIOS to enable E1.L config (enable VPP hotplug for 8 IIO PCIe ports in a Node). Note: starting from B020.P30 BIOS the HW Validation Test Only page is hidden. Please use old BIOS for alpha board or change to beta board. 2.HSD-ES 2103647907: after downgrading firmware R01.02.0007 release to R004 or R0003, a system will report SPS FW Health error in SEL. This is an expected behavior per PFR design. ME config settings are stored in the dynamic ME MFS region. PFR will not update dynamic region. W/A: Add "UpdateNvram" parameter for update command or set ME recovery jumper to force recovery of the ME cofnig settings in the dynamic region. Alternative workaround is to send an IPMI command after firmware update is complete:   ipmitool -I lanplus -H x.x.x.x -U YYY -P ZZZ -C 17 -b 6 -t 0x2c raw 0x2e 0xdf 0x57 0x01 0x00 0x02  where -H x.x.x.x represents the IP address of the Ethernet port dedicated to the server management -U YYY represents the user name for the BMC administartive account -P ZZZ represents the password for the BMC administartive account A system reboot is required for the changes to take effect. 3.HSD-ES 2103654859: After upgrade BIOS from R01.02.0006 to R01.02.0007, some BIOS options modified by using ITK/custom .CAP file will not retain their values after loading BIOS defaul by pressing key. W/A: AFter updating BIOS to R01.02.0007, create a new custom .CAP file with desired BIOS parameters and flash this .CAP file. 4.HSD-ES 2103654839: If the SMBIOS type0 string was modified by the ITK tool on a system running R01.02.0007 BIOS, the value of this string will be lost after downgrading to the BIOS R01.02.0006. W/A: None. BIOS R01.02.0006 does not support the SMBIOS type0 string. 5.HSD-ES 2103635229: If server with Secure Boot enabled is updated to the BIOS R01.02.0007, there will be a security warning message on the first reboot. W/A: Disable Secure Boot before updating to the BIOS R01.02.0007. After BIOS is updated, re-enable teh Secure Boot. 6.Please refer to TNP/CYP R01.01.0006 BIOS release note for common known issues and workaround. ================================================================================ CHANGE LIST ================================================================================ 01.02.0007 ================================================================================ This BIOS version is based on TNP/CYP R01.01.0006 BIOS with below code changes: Change BIOS ID to SE5C620.01.02.0007 Change copyright to 2023 [HSD-ES]:[2103643660] [AMP]Many PCIe items listed under EWS -> BIOS Configurations -> Integrated IO Configuration, cannot match the BIOS setup. [HSD-ES]:[2103654980] U.2 Retimer Slot ID info in SMBIOS Type 199 is different from the one in BIOS setup. [HSD-ES]:[2103655182] Inject Uncorrectable Non Fatal error to DIMM Rank 1 via WHEAHCT command, the SEL log show Rank 0. [HSD-ES]:[15011725935] BIOS should check the password once administrator password is set when performing BIOS online update. [HSD-ES]:[15011339171] SGX registration failed with BIOS 27P15(Regression) when online update BIOS. [HSD-ES]:[15011975987] PcdCpuSmmRestrictedMemoryAccess set FALSE in Whitley Sustaining phase. Update VROC driver v7.8.0.1012 for below 2 issues: 1. [HSD-ES]:[2103641997] [Sliver QRC]5 out of 10 nodes have "Management Subsys Health BMC FW Health | Sensor failure | Asserted" in SEL log whenreboot/AC/DC QRC test. 2. [HSD-ES]:[2103654855] [Q3 QSBR][QRC]"Voltage VR Watchdog Deasserted/Asserted" occurs during OS reset/DC cycling test (Fail rate: 2/700 cycles). From AMP R01.02.0006 to TNP/CYP R01.01.0006 BIOS include below code change: [BIOS Option change]:[CCB]:[3692][HSD-ES]:[15011178883] VMD PCIe address changed after FW update Add Advanced->PCI Configuration->Reset PCI Rebalance Data option, default is Disabled [CCB]:[3622][HSD-ES]:[15011020304][CCB3622] Enable CPU1 SlimSAS ports when CYP Interposer module is connected to CPU0 [HSD-ES]:[2103653665] After enable VMD, the NVME SSDs connected to CPU0 3x port are mapped as CPU0 PCIe 2x port in RSD Type 194 and EWS.(Regression) [HSD-ES]:[2103652088] Remove extra WhitleypcPkg definition [HSD-ES]:[2103652083] Correct Console Redirection expression for EWS." [HSD-ES]:[2103652819] No Password Salt or System Wide Salt Used" [HSD-ES]:[2103652714] Remove unnecessary option information. [HSD-ES]:[2103648335] PPR finish log is shown as Critical severity in EWS after inject CE to DIMM [HSD-ES]:[15011379852] Update default code reviewer for Whitley commercial Platform [HSD-ES]:[15011558718] When SMX is fused off then SINIT & BIOS ACMs SVNs should contain Reset Value in SE SVN MSR." Server-RC-0.4.2.0020 [Hsd-ES]:[2103652088] SUT does FRB2 reset when system under driver health manager screen of destroyed RAID volume. [Hsd-ES]:[2103651861] System cannot save the BIOS setting after load BIOS default by syscfg or sysfwupdt utility [Hsd-ES]:[15011215869] No Password Salt or System Wide Salt Used [Hsd-ES]:[22103651902] "Connector type" is wrong for M.2 NVMe SSD under EWS-->Storage information [Hsd-ES]:[15011209414] Intel Server BIOS Buffer overflow vulnerability. [Hsd-ES]:[15011347802] ME version is incorrect in BMC Event Log [BIOS Option change]:[CCB]:[3584][Hsd-ES]:[15010770843] [CCB3584] [BIOS] Redfish NIC config Knobs and SMBIOS type 42 for Redfish (Clone Purley CCB3158) Add Server Management->BMC LAN Configuration->"HI BMC Lan Configuration/HI Host LAN configuration" related settings [CCB]:[3473][Hsd-ES]:[15010873024] [CCB3473]Log SEL when OptionROM fails to verify with UEFI secure boot. Do not hang system boot or wait for key. [CCB]:[3609][Hsd-ES]:[15010770752] [CCB3609] [BMC/BIOS] Improve FRB2 behavior so on 3 attempts it is disabled [CCB]:[3535][Hsd-ES]:[15010770685] Change 'RAPL limit MSR Lock' knob value into Enable. [CCB]:[3610][Hsd-ES]:[15010770813] Improve Pfr panic checkpoint [Hsd-ES]:[2103644614] Correct Console Redirection expression for EWS. [Hsd-ES]:[2103650268] Correct callback issue. [Hsd-ES]:[2103644020] Correct SOL for Baseboard Mgmt2 option handling on CYP. [Hsd-ES]:[15010590176] Remove AMT complete SEL [Hsd-ES]:[15011182852] Enable PCIe ATS on Whitley BIOS [Hsd-ES]:[15011206608] Update RC version to 001B to align RP PLR3 Beta Candidate RC version 001C. [Hsd-ES]:[14016342444] M50CYP SUP R0005 does not report bad DIMM in POST message. [Hsd-ES]:[22014887190] Change PFR Watchdog Timer behavior to meet product requirements Problem. [Hsd-ES]:[15011062024] Change the GenITK tool from GenITK.exe into GenITK.py [Hsd-ES]:[15011040227] SUT can't log in the EWS when a user with a 20 characters password created in the BIOS setup [Hsd-ES]:[15010775402] ITK setting still can be applied successfully when PFR flash active BIOS failed. [Hsd-ES]:[16015331172] SATA and sSATA Driver depex [Hsd-ES]:[15011197631] Intel Server BIOS Buffer overflow vulnerability [Hsd-ES]:[2014627819] SPI PCIe config base after changing to 3G base [Hsd-ES]:[18019438530] Clear ITCCTRL23.rcb128 to align MS3IOSF RCB to PCIe RCB [Hsd-ES]:[15010809178] [Whitley] BMC received incorrect DIMM temperature data when DIMM SMBus met recovery situation (due to BIOS disabling the CLTT) [Hsd-ES]:[22014638487] RemoveInvalidPprEntry input parameter is Ch in Socket (0 to 7) and PprAddrSetup uses mc Channel (0 to 1)"" [Hsd-ES]:[22014623287] ICX Media Disabled Pmem module preventing reprovisioning of other modules on socket [Hsd-ES]:[22014700950] BSSA RMT fix for per bit margins [Hsd-ES]:[22014671673] Copyright tag shows old value in BIOS page. [Hsd-ES]:[22014638461] Block Decoder will not get mapped if DDR is mapped up to MMIOH [Hsd-ES]:[22014631175] Adding settings for DDR_2666 [Hsd-ES]:[22014638962] Remove HMRC WA from IPClean BIOS source [Hsd-ES]:[22014638861] The Memory RAS code may clean and corrupt the SystemMemory Map structure if the VariableSize being to a large value [Hsd-ES]:[22014638800] [PCI] Updating help text for Relaxed Ordering option. [Hsd-ES]:[22014630286] Silent Data Corruption occurs when Reversing and Forward ADDDC Rank Sparing [Hsd-ES]:[22014637898] Fix cpgcGblTrainingSetup.rwMode overwritten to read mode [Hsd-ES]:[18018607038] Change the way which buffer is passed between DXE and SMM drivers from UEFI variable to protocols [Hsd-ES]:[22014637927] EWL logging is missing for UCE PPR using failing DIMM [Hsd-ES]:[22014637905] Program Margin Read to reduced or increased values in case TSE EEPROM CRC failures [Hsd-ES]:[22014638380] when eMCA enabled MCE is not propagated to socket1 after socket0-punit catastrophic error injection [Hsd-ES]:[22014638893] Inclusion of SGX NVRAM manifest file in firmware build [Hsd-ES]:[14015874261] BaseResetSystemLinConstructor() is launched prior [Hsd-ES]:[22014698846] When SMX is fused off then SINIT & BIOS ACMs SVNs should contain Reset Value in SE SVN MSR. [Hsd-ES]:[15010270944] Memory ce skip ppr [Inclusive language]Replace deprecated terms in source code and remove some end of line space and tab. [CCB]:[3446] ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) below two case will allow to update itk cap. 1. ITK biosid matched with currently biosid 2. ITK biosid isn't matched with currently biosid, but matched with pch stage biosid. [Hsd-ES]:[15010599213] ITK resolution issue. Improve FRB- function ServerPlatformPkg/GenericIpmi: keep Getdeviceid () retries to 120s Update SVN version, change SVN version to 2. Enable PFR settings.for static region, enable RecoverDurings to 1, for BIOS dynamic region, only enable RecoverDuring3. [Hsd-ES]:[2103646731] The BIOS is not updated and there isn't SEL for the change after update ITK capsule with OOB method. [Hsd-ES]:[2103646616] The POST Err Sensor is wrong parsed as 'Event type 6f, offset 4' after system reboot [Hsd-ES]:[15010412593] The bifurcation setting value of M20464 riser card isn’t mapped with PCIE port info. [Hsd-ES]:[2103647675] After set the mirrored memory 20% mirrored above 4GB, current configuration is still shown as 'unknown' even change mirror mode to full mirror. [Hsd-ES]:[2103647670] After set the mirrored memory 20% mirrored above 4GB, there is unexpected message in SEL log and '85fc' error code occurs in error manager. [Hsd-ES]:[15010432715] Boot Failure with Adaptec Raid 3254/3258 on CYP Riser2 Slot1 [Hsd-ES]:[2103647720] BCM NIC FW not show in BMC Web NIC information page. [Hsd-ES]:[15010158887] Add support for Adaptec 3200 card. [Hsd-ES]:[15010031315] Correct the Comments message. [Hsd-ES]:[1509970724] Skip rankvls promotion when bankvls in single rank. [Hsd-ES]:[15010008515] If (RRL dev ==0) skip try Bank/Rank vls for the buddy bank/rank. [Hsd-ES]:[14015742100] Update on starve settings for VC0 deadlock. breaker for DDR4 scheduler deadlock bug Change copyright to 2022 Fix debug bios assert issue after clear cmos Change build output path into dynamic mode. Fix release path issue. [BIOS Option change] [Hsd-ES]:[2103646733] The current configuration will show as 'Unknown' after enable Mirror TAD0 and UEFI ARM Mirror Remove “UEFI ARM Mirror” at BIOS setup Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Removed [BIOS Option change] [Hsd-ES]:[2103646654] After flashed BIOS and reboot, there is critical error log in EWS for SPS FW Health and STATUS_LED blinking with orange. Service Managerment->MCTP Bus Owner->Value range"0-65535", "520" is default setting; [Hsd-ES]:[2103646622] The POST Err Sensor according ED value is shown as 0000 after system reboot [Hsd-ES]:[15010168104] [CCB3431] partial mirror mode can't be set successfully [Hsd-ES]:[2103646697] There isn't EWS log after change mirror mode value to dsiable or partial Mirror Mode. [Hsd-ES]:[2103646659] After inject CE to memory, there is only one Post Package Repair finish log. [Hsd-ES]:[2103646729] System always reset during POST after enable SGX and disable TME [Hsd-ES]:[2103646886] Only 19 PPR request logs are generated even inject over 21 times CE error to dimm no matter PPR type is Hard or Soft PPR. [Hsd-ES]:[2103646639] System can't power up after downgrade BIOS to R01.01.0004 through OOB. [Hsd-ES]:[2103646782] There is no SEL log and RED warning message shown on POST screen after flash a second mismatched ITK capsule. [Hsd-ES]:[22013752711] [Cherry-pick]ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. [Hsd-ES]:[16015331172] There is no VROC option ROM after enable VMD [Hsd-ES]:[2103646736] System will always show a message after Enable ARM Mirror and set a value for ARM Mirror percentage. [Hsd-ES]:[2103646941] With PPR type is Hard or Soft PPR setting, no PPR finished logs indicate correct memory slot/Rank after inject UCE error and has more unknown extra logs appear. [Hsd-ES]:[15010209598] [CCB3462] BIOS administrator password will not be bypassed when FORCE_EFI_BOOT or FORCE_EFI_BOOT_SILENT is detected. [Hsd-ES]:[2103647317] Some items can be changed&saved when enter BIOS setup with user password. [Hsd-ES]:[2103646245] System can't prompt 'Fatal Error : System Encounter A Stopper Error' after disable 'promote Warnings' option. add a tool for generate BIOS flash layout information. Update on starve settings for VC0 deadlock breaker for DDR4 scheduler deadlock bug" Fix Oob capsule generation failure. Due to completion timeout accessing main memory with RDIMM and PMEM in memory mode. 1) Adding PcdStarveTimer and PcdStarveThreshold with default values 0x12 and 0x4. 2) Adding PcdKeepStarveSettings to control if customer wants to keep BIOS settings(default should be TRUE) or let Pcode change the settings(FALSE) to new default settings(0x12 and 4). system hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" Correct the calculation under partial mirror by size [BIOS Option change] [Hsd-ES]:[1509848893] Remove “callback” for User Privilege at BIOS setup. Server Management->BMC LAN Configuration->User Configuration->Privilege->User/Operator/Administrator/No Access, No Access is default setting;(Remove "Callback") [BIOS Option change] [Hsd-ES]:[1509837959] Change "Uncore Freq" option range be 8 to 22 Advanced->Power & Performance->Uncore Power Management->Uncore Freq->Value range"8-22", "22" is default setting;(Uncore Freq Scaling need to set to disable before change Uncore Freq value) [BIOS Option change] [CCB]:[3504] [Hsd-ES]:[1509979164] CCB 3504 Enable OS Native AER SupporMenut in BIOS Setup Advanced->System Event Log->OS Native AER Support->Disabled/Enabled, Disabled is default setting; [BIOS Option change] [CCB]:[3431] [Hsd-ES]:[1509866088] CCB3431 Support Address range/partial memory mirroring feature on CYP/TNP BIOS Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Disabled/Full Mirror Mode/Partial Mirror Mode, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror TAD0->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Partial Mirror Mode->Partial Mirror X Size(GB)->"0" is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Enable->ARM Mirror percentage->"0" is default setting; [BIOS Option change] [CCB]:[3428] [Hsd-ES]:[1509980595] CCB3428 Expose PPR knob to commercial CYP/TNP BIOS (Sync up Purley CCB3027 to Whitley) Advanced->Memory Configuration->PPR Type->Hard PPR/Soft PPR/PPR Disabled, Hard PPR is default setting; [BIOS Option change] [CCB]:[3429] [Hsd-ES]:[1509980529] CCB3429 [BIOS-Align Purley] Enable Advanced MemTest for CYP/TNP BIOS(Sync up Purley CCB3178 to Whitley) Advanced->Memory Configuration->MemTest->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->MemTest Loops->"1" is default setting; Advanced->Memory Configuration->Adv MemTest Options->"0" is default setting; Advanced->Memory Configuration->Adv MemTest PPR Flow->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Retry After Repair->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Reset Failure Tracking List->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Adv MemTest Conditions->Disabled/Auto/Manual, Auto is default setting; [BIOS Option change] Remove "L1 only" option for PCIe ASPM Support (Global) option. Advanced->Integrated IO Configuration->PCIe Misc. Configuration->PCIe ASPM Support(Global)->Per invididual port/Disabled, Per individual port is default setting; [Hsd-ES]:[1509979099] [CCB]:[3443] CCB 3443 Port InSyde new features to BMC & BIOS Service Managerment->MCTP Bus Owner->Value range"0-9999", "0" is default setting; Service Managerment->MCTP Broadcast Cycle->Disabled/Enabled, Disabled is default setting; [Hsd-ES]:[1509980437] [CCB]:[3462]CCB3462 Bypass BIOS admin password when FORCE_EFI_BOOT or SILENT_FORCE_EFI_BOOT is detected [Hsd-ES]:[2103643900] [CCB]:[3524][CCB3524]Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[1509979269] [CCB]:[3422] CCB 3422 Sync up Purley RAS SEL log code to Whitley(Purley CCB 3245/3386/3388/3389 ) [Hsd-ES]:[1509979025] [CCB]:[3423]CCB 3423 [BIOS-Align Purley] Request PPR within SW Error Threshold Flow for new row entries [Hsd-ES]:[1509979201] [CCB]:[3446]CCB 3446 ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) [Hsd-ES]:[1509955510] Remove unused variables in PC_GENERATION_VOLATILE structure. [Hsd-ES]:[2103643984] Hide 'SOL for Baseboard Mgmt2' option on TNP. [Hsd-ES]:[1509988050] Setup and Help Items do not match SPEC and wrong spelling [Hsd-ES]:[1509925567] espi_smi failed in the log while run "chipsec_main -vv" in windows2022 with chipsec tool 1.7.1(New Tool) [Hsd-ES]:[1508596630] Add reserved variable for RP [Hsd-ES]:[14015052253] use AllocatePages to save SysSetup/EmulationSetting/CpuAndRevision into memory [Hsd-ES]:[22013740541] NXM Hole Range reported as Reserved with PRMRR setting 256GB with system memory populated with 768GB [Hsd-ES]:[22013771171] 3R2W interleave implementation has code dependency on DFX knob PcdBiosDfxKnobEnabled [Hsd-ES]:[18018321208] Enable si w/a 22013005570 [Hsd-ES]:[22013866480] [CPU 6330] BIOS hangs when MMCFG value is set to values as 1.5G and NUMA sets disabled. [Hsd-ES]:[22013803749] Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[22013801355] Clear CAP errors at boot in MC banks [Hsd-ES]:[15010169018] Add '_SM' in to IFWI name. [Hsd-ES]:[15010100174] Add buffer boundary check [Hsd-ES]:[1509882567] clear SNC registers in no-memory config [Hsd-ES]:[22013035870] System occurred iMC data parity error with MCACOD = 405 during stress [Hsd-ES]:[14015513993] System hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" [Hsd-ES]:[15010129062] Fix compiler warning [Hsd-ES]:[18019090175] Fixed detection MROM1 based on softstrap configuration [Hsd-ES]:[2103644190] WhitleyPcPkg/Network.dsc.inc: Set NETWORK_ISCSI_ENABLE to TRUE for supporting iSCSI [Hsd-ES]:[2103643272] "Resume On AC Power Loss" without roll back to ITK_Default value when clear CMOS. [Hsd-ES]:[1509848970] Intel(R) Virtualization Technology always disabled after command load default. [Hsd-ES]:[2103643269] Correct Riser1 retimer M20464-100 slot bifurcation function. [Hsd-ES]:[1509863439] ServerPlatformPkg/PlatformBootManagerLib: TPM firmware can't be updated successfully. [Hsd-ES]:[22013752711] ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. [BIOS Option change][Hsd-ES]:[1509744702] Set promote warning default to disable Advanced->Memory Configuration->Promote Warnings->Disabled/Enabled, Disabled is default setting; [BIOS Option change][Hsd-ES]:[22013088992], Public BIOS Setup Documentation does not include description of Syscfg accessible feature "Snooped Response Wait Time for Posted Prefetch" Advanced->Integration IO Configuration->Snoop Response Hold Off->Value range"0-0xf", "9" is default setting; [CCB]:[3393] Excludes SG1 Video as VGA device [Hsd-ES]:[1509687799] removing unsupported BIOS options from SETUP/ITK interface [Hsd-ES]:[2103635229] Add PTU key to DB [Hsd-ES]:[1509758508] Correct the help text pf Processor PCIe Link Speed [Hsd-ES]:[1509733004] Fix the ADDDC rank is wrong [Hsd-ES]:[2103643023] Core Count of SMBIOS type 4 will be changed after change active processor cores. [Hsd-ES]:[2103641737] Update 1U_2Slot_Riser2_SlimSAS_Interpose slot number. [Hsd-ES]:[18016159697] Update Mgphy Recipe 3.8 to add ATernate Attentuator Table set values Add depex for VMD driver [BIOS Option change][CCB]:[3343][Hsd-ES]:[1509325487], CCB 3343 Add option to turn ON/OFF->SET Uncore Frequency Scaling Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling->Disabled/Enabled, Enabled is default setting; Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling(Disabled)->Uncore Freq->Value range "8-22", "22" is default setting; [BIOS Option change][CCB]:[3438][Hsd-ES]:[1509325384], CCB 3438 [Whitley Q3'21]Expose RP AVX knobs to M50CYP/D50TNP BIOS Advanced->Power & Performance->CPU P State Control->AVX Licence Pre-Grant Override->Disable/Enabled, Disabled is default setting; [CCB]:[3430][Hsd-ES]:[1509325686][Whitley Q3'21][BIOS/BMC-Align Purley] Modify BIOS setup behavior around complex password(Sync up Purley CCB3356 to Whitley) [Hsd-ES]:[1509331555] Add Usb keyboard/mouse detected information in Diagnostic Screen [CCB]:[3433][Hsd-ES]:[1509325431] [Whitley Q3'21][BIOS-Align Purley]Check for #FORCE_EFI_BOOT_SILENT marker file in startup.nsh [CCB]:[3359][Hsd-ES]:[16012329091] 'Vendor' part is not getting updated using ITK Tool(CCB 3359). [Hsd-ES]:[2103640684] [6 SW CCB] The behavior is incorrect after NVRAM corruption. [Hsd-ES]:[2103641115] Bios option of "VMD for Direct Assign (CPU0, IOU1)" show on RISER1 VMD page is incorrect. [Hsd-ES]:[1509242103] Sync PfrShellCommands driver from WhitelyRpPkg [Hsd-ES]:[2103635892] Correct RSD SMBIOS Type 190 data. [Hsd-ES]:[2103639312] Correct Type 194 data. [Hsd-ES]:[1509334369] [CCB_3421]Modification of ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect, flash the modified ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect. [Hsd-ES]:[2103639009] Integrate American Pass BIOS changes ================================================================================ 01.02.0006 ================================================================================ This BIOS version is based on AMP 01.02.0004 code base and adds below code change: Update BIOS ACM and SINIT to 0020.P41 to fix HSD-ES: 2103647396, [Windows2022] Secure core AQ cert setup]AMP system can not boot to windows desktop if set firmware protection to on under widnows, it always reboots automatically after completing POST. ================================================================================ 01.02.0004 ================================================================================ This BIOS version is based on AMP 01.02.0003 code base and adds below code change: Update ICX XCC D0 microcode to 0x0d000311 to fix HSD-ES 14014984799. Modify BMC handshake code. Modify AMP RsdSmbiosDataUpdate () trigger event, follow TNP/CYP. Add MUX Reset GPIO pin TX State lock. ================================================================================ 01.02.0003 ================================================================================ This BIOS version is based on AMP 01.02.0002 code base and adds below code change: Update OpenSSL to 1.1.1j (security fix) from 0020.P37 code base. ================================================================================ 01.02.0002 ================================================================================ This BIOS version is based on AMP 01.02.0001 code base and adds below code change: HSD-ES: 1509723062, SSD can not be recognized in node CPU-0 when BMC update Retimer FW(1/13 nodes). Add MailBox register 0x607 to do handshake to notify BMC when can access SMBus MUX for HSBP CPLD/Retimer FW update operation. Enable GPP_C11 lock SMBus MUX function if no HSBP CPLD/Retimer FW update. ================================================================================ 01.02.0001 ================================================================================ This is the first "R" BIOS version: 01.02.0001 Changes in this version: HSD-ES: 2103639726, [AMP]System will auto reboot after disabling onboard video in EWS->BIOS Configurations->PCI Configuration. To support fix HSD 2103640179 and 1509360760, modify SPS scan rate period setting to 1s as WA. Add Intel fix for production line SUT hang at EE after CST test issue. Fix setup callback not execute issue. ================================================================================ B020.P30 ================================================================================ Change PFR Lock default state to enable. HW Validation Test Only page is hidden. AMP Gold build HW change: remove serial port B AMP Gold build HW change: remove internal USB port HSD-ES: 2103640970, There is no System Event Log Full (post code 84FF) shown in error manager when system event log is full. Sync TNP fix of HSD-ES: 1509348850, [L9][TNP]unexpected SEL detected during cycling test: NM Exception (#0x18) Informational event: NM Exception reports a Node Manager (NM) Exception event ================================================================================ A020.P30 ================================================================================ This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.30 Server-RC-0.2.2.0034 HSD-ES: 1509283474, VT-d / VT / TXT value cannot be changed via ITK. HSD-ES: 1508772959, Fix that DCM console display storage capacity is 0 in inventory information and health status is unknown. HSD-ES: 1508841934, No error info feedback when flash corrupted image with sysfwupdt(14.2 build9). HSD-ES: 1509267104, [CYP][CST]CYP OCP port Physical Slot Number (PSN) should display Slot 3. HSD-ES: 2103640373, Stop Bits is shown '0' in SPCR table. HSD-ES: 14014151709, [ICX] Increase rrsr for channels that have roundtrip > 0x5a. HSD-ES: 22013162072, [ICX_FW_EVAL] SUT hungs while running Fisher tool command in RHEL OS. HSD-ES: 2103639620, [ICX]SMBIOS type 9, 192 and 200 are incorrect with retimer(PBA M20464-100) attached.(Q3QSBR). HSD-ES: 22013035870, System occurred iMC data parity error with MCACOD = 405 during stress. Check if dedicated BMC lan port exist then show on Diag screen. ================================================================================ A020.P29 ================================================================================ This release is mapping to PC daily build: WHITLEY.0.PCB.0020.P.29 Server-RC-0.2.2.0033 Please refer to ReleaseNotes_0020P29_ICX.txt for change list of 0020.P29 Add VMD Direct Assign options to AMP VMD ports. ================================================================================ A020.P28 ================================================================================ This release is based on PC daily build: WHITLEY.0.PCB.0020.P.28 Server-RC-0.2.2.0032 HSD-ES: 2103640187, [AMP] PWRDIS doesn't control for VPP -- bit 2 HSD-ES: 18016147518, Mask EB errors from being escalated to Receiver Error HSD-ES: 1509142909, No BPM scrtm error. HSD-ES: 1509019075, Sync WhitleyPcPkg with WhitleyRpPkg code HSD-ES: 1509206537, CCB 3340 Root port help string not match the option name. HSD-ES: 2103640145, In BMC force update mode,BIOS/ME inband update fail with sysfwupdt tool. HSD-ES: 2103640245, Gray out setup Sub NUMA item if CPU core numbers is less than 12. HSD-ES: 22011887647, add scrtm error check. Gen3 Ph3 TxEq Manual Precursor/ Postcursor default value change. HSD-ES: 22012862056, PCIe Dfx Wa to support MPS configs like 512 x8 Gen1/2/3. Merge AMP code into Whitley trunk. HSD-ES: 2103640169, ITK BIOS option doesn't match "intel tool support list" form Spec_v1.02_Premark03252021. HSD-ES: 22011887647, Support Granular SCRTM error handling. HSD-ES: 14014078016, Modify NM core disable algorithm HSD-ES: 18016118881, Set rx_dword144 register fields after MGPHY recipe application and before link training. HSD-ES: 2103640245, Gray out setup Sub NUMA item if CPU core numbers is less than 12. HSD-ES: 1509185597, Whitley KW issue reported when merging AMP code. HSD-ES: 1509173438, Correct PCIe ASPM Support option setting. HSD-ES: 22011837665, [ICX] [RAS] [ADDDC] Reverse and Remaping Bank VLS is causing system hang. ================================================================================ A020.P25 ================================================================================ Merge code change to fix 2103639051 [ICX][CCB 3327]SUT will not auto power on at second T-1 state after flash BIOS recovery region via Sysfwupdt_V14_2_Build9. ================================================================================ B020.P24 ================================================================================ 1.Enable GPIO detect BP feature for AMP beta board, and add setup item to force E1.L BP for alpha board. 2.EWS's Storage information page have incorrect information when BIOS enable VMD. ================================================================================ A020.P24 ================================================================================ 1.Please refer to ReleaseNotes_0020P24_ICX.txt for 0020.P24 BIOS common change list. 2.HSD-ES:2103639570 : There is no SEL log for UPI CE when inject UPI correctable error. 3.HSD-ES:2103639719 WHLK detect 10*usb3.0 port but AMP only have 3*usb3.0 port. 4.HSD-ES:2103639710: 'SOL for Baseboard Mgmt2' is redundant option in BIOS setup for AMP. 5.HSD-ES:2103639712: Help text and BIOS setup spec of System Event Log is shown View/Configure 'memory' information. 6.HSD-ES:2103639714: The subitems of PCIE SSD port's value can't be choosen after set Volume Management Device option to "Enabled". 7.Fix Setup IIO NTB page not correct. 8.Fix Setup Link Speed page not correct. ================================================================================ A020.P23 ================================================================================ 1.Please refer to ReleaseNotes_0020P22_ICX.txt for 0020.P22 BIOS common change list. 0020.P23 BIOS fix HSD-ES:210363907: Current Active Processor Cores is not changed after change Active Processor Cores via syscfg. 2.HSD-ES:2103639448: System can't boot in tboot OS and reboot at "Loading initial ramdisk ¡K" screen when enable TXT. 3.HSD-ES:2103639596: System auto reboot when run "getsec64.efi -l SENTER -i" with enable TXT. 4.HSD-ES:2103639371: [AMP][PSU] SMBAlert# signal kept low but back to high level when AC plug out of PSU4. 5.Update RSD SMBIOS Type194 and Type199 for AMP. ================================================================================ A020.P20 ================================================================================ 1.Please refer to ReleaseNotes_0020P20_ICX.txt for 0020.P20 BIOS common change list. One exception is HSD-ES:1508887608, Change PFR LOCK to enabled by default. AMP remain PFR Lock disable in development phase. 2.HSD-ES:2103639219: SMBIOS Type 8 is incorrect. 3.HSD-ES:2103639302: The 'PFR Provision' default value in BIOS setup and ITK isn't match the BIOS setup spec v1.02 requirment. 4.HSD-ES:2103639129: The 'USB front ports enable' option is listed at BIOS setup but system doesn't support it. ================================================================================ B020.P17 ================================================================================ 1.Please refer to ReleaseNotes_0020P17_ICX.txt for 0020.P17 BIOS common change list. 2.HSD-ES:2103639026: U.2 HDD LED status is incorrect when RAID Fail/set "Locate LED" to "ON" in BIOS, SPEC request is "Amber" but actual is "OFF". 3.HSD-ES:2103638974: The Platform_ID D50AMP in BIOS setup is incorrect. 4.HSD-ES:2103639009: POST screen show incorrect Baseboard NIC information. 5.Enable setup HW Validation page. ================================================================================ A020.P17 ================================================================================ 1.Please refer to ReleaseNotes_0020P17_ICX.txt for 0020.P17 BIOS common change list. 2.AMP BIOS version rule change to A0xx.xxx. Ex: AMP BIOS A020.P17 is based on TNP/CYP 0020.P17 code. 3.Fix serial port B is default disabled and setup item is hidden. 4.In setup PFR page, CPLD Common Version files show wrong string TNPxxx. 5.Add setup VMP settings for BP PCIe SSD. For current board cannot determine which BP installed, force E1.L BP (4 VMD port per CPU). ================================================================================ 1019.D39 ================================================================================ 1.Initial release for AmericanPass board. 2.Based on TNP/CYP 0019.D39 BIOS and modify below: PFR provision default disable. DCI default enable. 3.This release is mapping to RP daily build: WHITLEY.0.RPB.0019.d.39 4.RP release Reference code version: Server-RC-0.2.1.0068