================================================================================ Intel(R) Server Platform BIOS Release Notes ================================================================================ INTEL(R) Server Boards and Systems Intel Corporation 2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA ================================================================================ DATE : March 11, 2022 TO : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers SUBJECT : BIOS Release notes ================================================================================ LEGAL INFORMATION ================================================================================ Information in this document is provided in connection with Intel Products and for the purpose of supporting Intel developed server boards and systems. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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Copyright (C) 2022 Intel Corporation. ================================================================================ ABOUT THIS RELEASE ================================================================================ Build Stamp: SE5C620.86B.01.01.0005.2202160810 Build Date: February 16, 2022 ================================================================================ Supported Platforms ================================================================================ M50CYP Family R01010005_CoyotePass_LBG_ICX.bin Checksum: 0x5B5CBA6B SFID offset: 0x7B8024 SFID value: 0x3de62f3d D50TNP Family R01010005_TennesseePass_LBG_ICX.bin Checksum: 0x5B57D49B SFID offset: 0x7B8024 SFID value: 0x96a5a7e ================================================================================ BIOS COMPONENTS/CONTENTS ================================================================================ Processors supported: Intel(R) Xeon(R) Scalable Processors 3rd Generation Microcode versions: CPUID Version Status 606a4 0x0b000280 (ICX-SP HCC L0) 606a5 0x0c0002f0 (ICX-SP XCC C0) 606a6 0x0d000332 (ICX-SP XCC D0/D1/D2 & HCC M1) SATAAHCI: v2.00i VROCSataEfi: v7.6.0.1012 VROCsSataEfi: v7.6.0.1012 BIOSACM: Production,v1.0.E_LBG SINIT: Production,v1.0.F_LBG NvmDimmDriver: v02.00.00.3885 NvmDimmHii: v02.00.00.3885 ASTVBIOS: v1.09 VMDVROC2: v7.6.0.1012 VMDVROC1: v7.6.0.1012 SPS: 04.04.04.062 PCH PFR SVN: 02 ================================================================================ INSTALLATION NOTES ================================================================================ WARNING: It is very important to follow these instructions as they are written. Failure to update using the proper procedure may cause damage to your system. Firmware Update Tools: Sysfwupdt User can update BIOS flash image via either of the follow methods... A. UEFI sysfwupdt 1. Power on system, press F2 enter BIOS setup and goto Main > PFR page, set PFR provision to enable. 2. Press F10 to save and reboot. 3. During POST, press F2 to enter BIOS setup again, goto Main > PFR page, PFR Provision change to grey and can't be chosen, PFR Provision Status change to Provisioned. 4. Copy the entire contents of the IWFI package to the HDD or USB flash drive. (All of the files in the package must reside in the same directory.) 5. Boot to UEFI Shell, then change the Shell to mapped device file system Example: Shell> fs0: (or fs1:) 6. Run UpdBIOS_CYP.nsh (or UpdBIOS_TNP.nsh). 7. Reboot system after the update is completed. 8. Do *NOT* interrupt the BIOS POST during the first boot. ================================================================================ SVN_BYPASS Jumper ================================================================================ SVN_BYPASS Jumper: Platform not support flash PCH capsule with high SVN to lower SVN, when the jumper is set, It will be allowed PCH capsule file can be online updated to lower SVN one. 1. AC off. 2. Switch the SVN_BYPASS jumper. Details regarding the jumper ID and location can be obtained from the Board EPS for that Platform. 3. Power ON the system, boot to BIOS setup. 4. At Main->PFR page, check "PCH SVN Bypass Jumper Status: ON". 5. Boot to shell, flash PCH capsule by command: sysfwupdt.efi -u xxx.bin -recovery. ================================================================================ IMPORTANT NOTICE ================================================================================ 1. BIOS R01.01.0003 must work with BMC2.81 and CPLD v3p3, otherwise it will have known issues: 2103638642/2103638732/2103639051/2103639969. 2. When update target BIOS which PCH SVN is higher than current verion, need add "-recovery" parameter at flash command. (e.g. sysfwupdt.efi -u xxx.bin -recovery) 3. From BIOS R01.01.0004 has fixed HSD2103635229, need online update BIOS w/ secure boot disable or Update BIOS w/ UpdateNvram parameter and later to make sure the fix has been taken effect. 4. 2103635229 There is secure boot policy warning message shown after online flash BIOS with secureboot enabled. 5. From BIOS R01.01.0005 it has updated PCH SVN to 02, need add "-recovery" parameter when update BIOS which has lower SVN to R01.01.0005 or higher. (e.g. sysfwupdt.efi -u xxx.bin -recovery). ================================================================================ KNOWN ISSUES/WORKAROUND ================================================================================ 1.[Hsd-ES]:[2103628066] Windows 2019 will BSOD when enable VT-D.Please enable "Limit CPU PA to 46 bits" when boot to Windows 2019 with Intel(R) VT for Directed I/O enabled. 2.[Hsd-ES]:[1509669610] There is one critical "Force ME Recovery" event in SEL after online flash BIOS from R01010003 to later version via sysfwupdt.efi(regression issue) 3.[Hsd-ES]:[16015331615] Prompt message appears when online update BIOS from R01.01.0004 to later with ASPM is "L1 only" setting. W/A:Online update BIOS by UpdateNvram parameter or press F9 after online update BIOS. 4.[Hsd-ES]:[2103646748] 'PPR' option default setting is disabled after online flash BIOS from R01.01.0004 to later. W/A:Online update BIOS by UpdateNvram parameter or press F9 after online update BIOS. 5.[Hsd-ES]:[2103647928] Enter Windows 2022 OS and inject UCE, there are many unexpected log for 'OEM timestamped' and 'Event type 6f, offset 1' generated. 6.[Hsd-ES]:[2103647907] Downgrade SUP or SFUP from R01.01.0005 release to R01.01.0004 or R01.01.0003 , system will report SPS FW Health error in sellog. W/A:1. Downgrade SUP or SFUP with UpdateNvram when flash BIOS 2. AC off, set ME jumper to force recovery mode first, AC on boot system then AC off and set ME jumper to normal. 3. using IPMI command to force ME recovery mode: ipmitool.exe -H x.x.x.x(BMC IP) -U xxx(BMC User name) -P xxxx(BMC User password) -I lanplus -b 6 -t 0x2c raw 0x2e 0xdf 0x57 1 0 2 7.[Hsd-ES]:[2103648506] System will halt at POST and report 'IERR-Non boot core FIVR fault' in sel after set disable CPU core No. with IPMI command. 8.[Hsd-ES]:[2103649593] Flash the modified ITK cap BIOS, BIOS option does not keep ITK cap settings instead to be BIOS default after press F9 to load default. ================================================================================ CHANGE LIST ================================================================================ R01.01.0005 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0005 [CCB]:[3446] ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) below two case will allow to update itk cap. 1. ITK biosid matched with currently biosid 2. ITK biosid isn't matched with currently biosid, but matched with pch stage biosid. [Hsd-ES]:[15010599213] ITK resolution issue. Improve FRB- function ServerPlatformPkg/GenericIpmi: keep Getdeviceid () retries to 120s Update SVN version, change SVN version to 2. Enable PFR settings.for static region, enable RecoverDurings to 1, for BIOS dynamic region, only enable RecoverDuring3. [Hsd-ES]:[2103646731] The BIOS is not updated and there isn't SEL for the change after update ITK capsule with OOB method. [Hsd-ES]:[2103646245] System can't prompt 'Fatal Error : System Encounter A Stopper Error' after disable 'promote Warnings' option. [Hsd-ES]:[2103646616] The POST Err Sensor is wrong parsed as 'Event type 6f, offset 4' after system reboot [Hsd-ES]:[15010209598] [CCB3462] BIOS administrator password will not be bypassed when FORCE_EFI_BOOT or FORCE_EFI_BOOT_SILENT is detected. [Hsd-ES]:[15010412593] The bifurcation setting value of M20464 riser card isn’t mapped with PCIE port info. [Hsd-ES]:[2103647675] After set the mirrored memory 20% mirrored above 4GB, current configuration is still shown as 'unknown' even change mirror mode to full mirror. [Hsd-ES]:[2103647670] After set the mirrored memory 20% mirrored above 4GB, there is unexpected message in SEL log and '85fc' error code occurs in error manager. [Hsd-ES]:[15010432715] Boot Failure with Adaptec Raid 3254/3258 on CYP Riser2 Slot1 [Hsd-ES]:[2103647720] BCM NIC FW not show in BMC Web NIC information page. [Hsd-ES]:[15010158887] Add suppor for Adaptec 3200 card. [Hsd-ES]:[15010031315] Correct the Comments message. [Hsd-ES]:[1509970724] Skip rankvls promotion when bankvls in single rank. [Hsd-ES]:[15010008515] If (RRL dev ==0) skip try Bank/Rank vls for the buddy bank/rank. [Hsd-ES]:[14015742100] Update on starve settings for VC0 deadlock. breaker for DDR4 scheduler deadlock bug Change copyright to 2022 Fix debug bios assert issue after clear cmos Change build output path into dynamic mode. Fix release path issue. [BIOS Option change] [Hsd-ES]:[2103646733] The current configuration will show as 'Unknown' after enable Mirror TAD0 and UEFI ARM Mirror Remove “UEFI ARM Mirror” at BIOS setup Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Removed [BIOS Option change] [Hsd-ES]:[2103646654] After flashed BIOS and reboot, there is critical error log in EWS for SPS FW Health and STATUS_LED blinking with orange. Service Managerment->MCTP Bus Owner->Value range"0-65535", "520" is default setting; [Hsd-ES]:[1509988050] Setup and Help Items do not match SPEC and wrong spelling [Hsd-ES]:[2103646622] The POST Err Sensor according ED value is shown as 0000 after system reboot [Hsd-ES]:[15010168104] [CCB3431] partial mirror mode can't be set successfully [Hsd-ES]:[2103646697] There isn't EWS log after change mirror mode value to dsiable or partial Mirror Mode. [Hsd-ES]:[2103646659] After inject CE to memory, there is only one Post Package Repair finish log. [Hsd-ES]:[2103646729] System always reset during POST after enable SGX and disable TME [Hsd-ES]:[2103646886] Only 19 PPR request logs are generated even inject over 21 times CE error to dimm no matter PPR type is Hard or Soft PPR. [Hsd-ES]:[2103646639] System can't power up after downgrade BIOS to R01.01.0004 through OOB. [Hsd-ES]:[2103646782] There is no SEL log and RED warning message shown on POST screen after flash a second mismatched ITK capsule. [Hsd-ES]:[22013752711] [Cherry-pick]ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. [Hsd-ES]:[16015331172] There is no VROC option ROM after enable VMD [Hsd-ES]:[2103646736] System will always show a message after Enable ARM Mirror and set a value for ARM Mirror percentage. [Hsd-ES]:[2103646941] With PPR type is Hard or Soft PPR setting, no PPR finished logs indicate correct memory slot/Rank after inject UCE error and has more unknown extra logs appear. [Hsd-ES]:[15010209598] [CCB3462] BIOS administrator password will not be bypassed when FORCE_EFI_BOOT or FORCE_EFI_BOOT_SILENT is detected. [Hsd-ES]:[2103647317] Some items can be changed&saved when enter BIOS setup with user password. [Hsd-ES]:[2103646245] System can't prompt 'Fatal Error : System Encounter A Stopper Error' after disable 'promote Warnings' option. add a tool for generate BIOS flash layout information. Update on starve settings for VC0 deadlock breaker for DDR4 scheduler deadlock bug" Fix Oob capsule generation failure. Due to completion timeout accessing main memory with RDIMM and PMEM in memory mode. 1) Adding PcdStarveTimer and PcdStarveThreshold with default values 0x12 and 0x4. 2) Adding PcdKeepStarveSettings to control if customer wants to keep BIOS settings(default should be TRUE) or let Pcode change the settings(FALSE) to new default settings(0x12 and 4). system hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" Correct the calculation under partial mirror by size [BIOS Option change] [Hsd-ES]:[1509848893] Remove “callback” for User Privilege at BIOS setup. Server Management->BMC LAN Configuration->User Configuration->Privilege->User/Operator/Administrator/No Access, No Access is default setting;(Remove "Callback") [BIOS Option change] [Hsd-ES]:[1509837959] Change "Uncore Freq" option range be 8 to 22 Advanced->Power & Performance->Uncore Power Management->Uncore Freq->Value range"8-22", "22" is default setting;(Uncore Freq Scaling need to set to disable before change Uncore Freq value) [BIOS Option change] [CCB]:[3504] [Hsd-ES]:[1509979164] CCB 3504 Enable OS Native AER SupporMenut in BIOS Setup Advanced->System Event Log->OS Native AER Support->Disabled/Enabled, Disabled is default setting; [BIOS Option change] [CCB]:[3431] [Hsd-ES]:[1509866088] CCB3431 Support Address range/partial memory mirroring feature on CYP/TNP BIOS Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Disabled/Full Mirror Mode/Partial Mirror Mode, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror TAD0->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->Mirror Mode->Partial Mirror Mode->Partial Mirror X Size(GB)->"0" is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->UEFI ARM Mirror->Enable->ARM Mirror percentage->"0" is default setting; [BIOS Option change] [CCB]:[3428] [Hsd-ES]:[1509980595] CCB3428 Expose PPR knob to commercial CYP/TNP BIOS (Sync up Purley CCB3027 to Whitley) Advanced->Memory Configuration->PPR Type->Hard PPR/Soft PPR/PPR Disabled, Hard PPR is default setting; [BIOS Option change] [CCB]:[3429] [Hsd-ES]:[1509980529] CCB3429 [BIOS-Align Purley] Enable Advanced MemTest for CYP/TNP BIOS(Sync up Purley CCB3178 to Whitley) Advanced->Memory Configuration->MemTest->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->MemTest Loops->"1" is default setting; Advanced->Memory Configuration->Adv MemTest Options->"0" is default setting; Advanced->Memory Configuration->Adv MemTest PPR Flow->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Retry After Repair->Disabled/Enabled, Enabled is default setting; Advanced->Memory Configuration->Adv MemTest Reset Failure Tracking List->Disabled/Enabled, Disabled is default setting; Advanced->Memory Configuration->Adv MemTest Conditions->Disabled/Auto/Manual, Auto is default setting; [BIOS Option change] Remove "L1 only" option for PCIe ASPM Support (Global) option. Advanced->Integrated IO Configuration->PCIe Misc. Configuration->PCIe ASPM Support(Global)->Per invididual port/Disabled, Per individual port is default setting; [Hsd-ES]:[1509979099] [CCB]:[3443] CCB 3443 Port InSyde new features to BMC & BIOS Service Managerment->MCTP Bus Owner->Value range"0-9999", "0" is default setting; Service Managerment->MCTP Broadcast Cycle->Disabled/Enabled, Disabled is default setting; [Hsd-ES]:[1509980437] [CCB]:[3462]CCB3462 Bypass BIOS admin password when FORCE_EFI_BOOT or SILENT_FORCE_EFI_BOOT is detected [Hsd-ES]:[2103643900] [CCB]:[3524][CCB3524]Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[1509979269] [CCB]:[3422] CCB 3422 Sync up Purley RAS SEL log code to Whitley(Purley CCB 3245/3386/3388/3389 ) [Hsd-ES]:[1509979025] [CCB]:[3423]CCB 3423 [BIOS-Align Purley] Request PPR within SW Error Threshold Flow for new row entries [Hsd-ES]:[1509979201] [CCB]:[3446]CCB 3446 ITK modified BIOS should be done at same time as standard BIOS. (no reboot in between) [Hsd-ES]:[1509955510] Remove unused variables in PC_GENERATION_VOLATILE structure. [Hsd-ES]:[2103643984] Hide 'SOL for Baseboard Mgmt2' option on TNP. [Hsd-ES]:[1509988050] Setup and Help Items do not match SPEC and wrong spelling [Hsd-ES]:[1509925567] espi_smi failed in the log while run "chipsec_main -vv" in windows2022 with chipsec tool 1.7.1(New Tool) [Hsd-ES]:[1508596630] Add reserved variable for RP [Hsd-ES]:[14015052253] use AllocatePages to save SysSetup/EmulationSetting/CpuAndRevision into memory [Hsd-ES]:[22013740541] NXM Hole Range reported as Reserved with PRMRR setting 256GB with system memory populated with 768GB [Hsd-ES]:[22013771171] 3R2W interleave implementation has code dependency on DFX knob PcdBiosDfxKnobEnabled [Hsd-ES]:[1509723062] SMBIOS Mux Pin Handling and CPLD/Retimer FW update design enhancement . [Hsd-ES]:[18018321208] Enable si w/a 22013005570 [Hsd-ES]:[22013866480] [CPU 6330] BIOS hangs when MMCFG value is set to values as 1.5G and NUMA sets disabled. [Hsd-ES]:[22013803749] Asset Tag String is null in SMBIOS Type17. [Hsd-ES]:[22013801355] Clear CAP errors at boot in MC banks [Hsd-ES]:[15010169018] Add '_SM' in to IFWI name. [Hsd-ES]:[15010100174] Add buffer boundary check [Hsd-ES]:[1509882567] clear SNC registers in no-memory config [Hsd-ES]:[22013035870] System occurred iMC data parity error with MCACOD = 405 during stress [Hsd-ES]:[14015513993] System hang on post during configuring memories if install DIMM on "slot A1~A6 + B1~B6" [Hsd-ES]:[15010129062] Fix compiler warning [Hsd-ES]:[18019090175] Fixed detection MROM1 based on softstrap configuration Switch to new branch [wlypc_qsbr_rel] (release/wlypc_2021_intel_23d50) Lock SMBIOS Mux Reset GPIO Pin TX State. Server-RC-0.4.2.0012 ================================================================================ R01.01.0004 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0004 Update XCC D0/D1/D2 & HCC M1 microcode to 0x0d000311 [Hsd-ES]:[2103644190] WhitleyPcPkg/Network.dsc.inc: Set NETWORK_ISCSI_ENABLE to TRUE for supporting iSCSI [Hsd-ES]:[2103643272] "Resume On AC Power Loss" without roll back to ITK_Default value when clear CMOS. [Hsd-ES]:[1509848970] Intel(R) Virtualization Technology always disabled after command load default. [Hsd-ES]:[2103643269] Correct Riser1 retimer M20464-100 slot bifurcation function. [Hsd-ES]:[1509863439] ServerPlatformPkg/PlatformBootManagerLib: TPM firmware can't be updated successfully. [Hsd-ES]:[22013752711] ServerPlatformPkg/Platform/Dxe/MemorySubClass: The Partition Width of SMBIOS type 19 are not match channel way of SAD with specific memory config. [BIOS Option change][Hsd-ES]:[1509744702] Set promote warning default to disable Advanced->Memory Configuration->Promote Warnings->Disabled/Enabled, Disabled is default setting; [BIOS Option change][Hsd-ES]:[22013088992], Public BIOS Setup Documentation does not include description of Syscfg accessible feature "Snooped Response Wait Time for Posted Prefetch" Advanced->Integration IO Configuration->Snoop Response Hold Off->Value range"0-0xf", "9" is default setting; [CCB]:[3393] Excludes SG1 Video as VGA device [Hsd-ES]:[1509687799] removing unsupported BIOS options from SETUP/ITK interface [Hsd-ES]:[2103635229] Add PTU key to DB [Hsd-ES]:[1509758508] Correct the help text pf Processor PCIe Link Speed [Hsd-ES]:[1509733004] Fix the ADDDC rank is wrong [Hsd-ES]:[2103643023] Core Count of SMBIOS type 4 will be changed after change active processor cores. [Hsd-ES]:[2103641737] Update 1U_2Slot_Riser2_SlimSAS_Interpose slot number. [Hsd-ES]:[18016159697] Update Mgphy Recipe 3.8 to add ATernate Attentuator Table set values Add depex for VMD driver [BIOS Option change][CCB]:[3343][Hsd-ES]:[1509325487], CCB 3343 Add option to turn ON/OFF->SET Uncore Frequency Scaling Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling->Disabled/Enabled, Enabled is default setting; Advanced->Power & Performance->Uncore Power Management->Uncore Freq Scaling(Disabled)->Uncore Freq->Value range "8-22", "22" is default setting; [BIOS Option change][CCB]:[3438][Hsd-ES]:[1509325384], CCB 3438 [Whitley Q3'21]Expose RP AVX knobs to M50CYP/D50TNP BIOS Advanced->Power & Performance->CPU P State Control->AVX Licence Pre-Grant Override->Disable/Enabled, Disabled is default setting; [CCB]:[3430][Hsd-ES]:[1509325686][Whitley Q3'21][BIOS/BMC-Align Purley] Modify BIOS setup behavior around complex password(Sync up Purley CCB3356 to Whitley) [Hsd-ES]:[2103639726] Correct method to fetch VideoExist variable. [Hsd-ES]:[1509423750] system will hang EE after running CST. [Hsd-ES]:[1509331555] Add Usb keyboard/mouse detected information in Diagnostic Screen [CCB]:[3433][Hsd-ES]:[1509325431] [Whitley Q3'21][BIOS-Align Purley]Check for #FORCE_EFI_BOOT_SILENT marker file in startup.nsh [CCB]:[3359][Hsd-ES]:[16012329091] 'Vendor' part is not getting updated using ITK Tool(CCB 3359). [Hsd-ES]:[2103640684] [6 SW CCB] The behavior is incorrect after NVRAM corruption. [Hsd-ES]:[2103639726] Add COMMON VOLATILE variable VideoExist. [Hsd-ES]:[2103641115] Bios option of "VMD for Direct Assign (CPU0, IOU1)" show on RISER1 VMD page is incorrect. [Hsd-ES]:[1509242103] Sync PfrShellCommands driver from WhitelyRpPkg [Hsd-ES]:[2103635892] Correct RSD SMBIOS Type 190 data. [Hsd-ES]:[2103639312] Correct Type 194 data. [Hsd-ES]:[1509334369] [CCB_3421]Modification of ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect, flash the modified ITK BIOS Gen3 Override mode&Gen4 Override mode -> Ph3 TxEq Precursor& Ph3 TxEq Postcursor options does not take effect. [Hsd-ES]:[2103639009] Integrate American Pass BIOS changes [Hsd-ES]:[1509283474] VT-d / VT / TXT value cannot be changed via ITK [Hsd-ES]:[1508772959] Fix that DCM console display storage capacity is 0 in inventory information and health status is unknown [Hsd-ES]:[1508841934] No error info feedback when flash corrupted image with sysfwupdt(14.2 build9) [Hsd-ES]:[1509267104] Correct OCP port slot number. [Hsd-ES]:[2103639620] Correct slot number per riser accordingly. [Hsd-ES]:[2103639625] [ICX]SMBIOS type 9, 192 and 200 are incorrect with retimer(PBA K81522-101) attached.(Q3QSBR) [Hsd-ES]:[2103640322] Stop Bits is 0 on ACPI SPCR table. [Hsd-ES]:[14014136819] Incorrect pointer caused while loop hang. [BIOS Option change][CCB]:[3421][Hsd-ES]:[1509075812]Gen3 Ph3 TxEq Manual Precursor/ Postcursor default value change. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->UniPhy/Manual, UniPhy is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->MgPhy/Manual Ph3, MgPhy is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->Ph3 TxEq Precursor->Value range"0-63", "9" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen3 Override mode->Ph3 TxEq Postcursor->Value range"0-63", "4" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->Ph3 TxEq Precursor->Value range"0-63", "0" is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->Gen4 Override mode->Ph3 TxEq Postcursor->Value range"0-63", "13" is default setting; [BIOS Option change][CCB]:[3407][Hsd-ES]:[14013786502], VMD Direct Assign Not Implemented in the Coyote Pass BIOS Advanced->Integration IO Configuration->Volume Management Device->XXX Volume Management Device(CPUX XXX)->VMD for Direct Assign(XXX)->Disabled/Enabled, Disabled is default setting; [BIOS Option change][CCB]:[3340]Patch3:Implement Per Port ASPM setting feature. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->PCIe ASPM Support->Disabled/L1 Only, "L1 Only" is default setting; [BIOS Option change][CCB]:[3367][Hsd-ES]:[1509035691][CCB3367] Add bank threshold function. Advanced->Memory Configuration->Memory RAS and Performance Configuration->Triger SW Error Threshold->Enabled/Disabled, Enabled is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->SW Per Bank Threshold->Value range "1-0x7FFF", "4" is default setting; Advanced->Memory Configuration->Memory RAS and Performance Configuration->SW Correctable Error Time Window->Value range "0-24", "24" is default setting; [BIOS Option change][CCB]:[3366][Hsd-ES]:[16012325043], [CCB3366]Request to add per-port knob for ECRC configuration in BIOS menu. Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->ECRC Generation->Disabled/Enabled, Disabled is default setting; Advanced->Integration IO Configuration->PCIe Misc. Configuration->Socket X Configuration->Port XX->ECRC Check->Disabled/Enabled, Disabled is default setting; [BIOS Option change][CCB]:[3346][Hsd-ES]:[1509035633], Part of CCB 3346 Support secure-core in BIOS Advanced->Integration IO Configuration->Pre-boot DMA Protection->Enabled/Disabled, Disabled is default setting;(Change this option need set Intel(R) VT for Directed I/O to Enable first) [Hsd-ES]:[1509243170], DMA Control Opt-in Flag and Pre-boot DMA Protection should be hidden when VT-D set to disable [Hsd-ES]:[2103639614], SFUP FW update will not record BIOS update information event [Hsd-ES]:[1509019075], Sync WhitleyPcPkg with WhitleyRpPkg code [Hsd-ES]:[1509206537], CCB 3340 Root port help string not match the option name [Hsd-ES]:[2103640145], In BMC force update mode,BIOS/ME inband update fail with sysfwupdt tool. [Hsd-ES]:[2103640245], Patch 2 .Gray out setup Sub NUMA item if CPU core numbers is less than 12. [Hsd-ES]:[2103640169], ITK BIOS option doesn't match "intel tool support list" form Spec_v1.02_Premark03252021. [Hsd-ES]:[1509185597], Whitley KW issue reported when merging AMP code. [Hsd-ES]:[1509173438], Correct PCIe ASPM Support option setting. [Hsd-ES]:[1509173445], CCB 3366/CCB3340:Use the ITK tool to change the values of the ECRC and ASPM options under each root port under the BIOS Advanced > Inegrated IO Configuration > PCIe Misc.Configuration interface, [Hsd-ES]:[16013309544], set_biosconfig command failed and with "ProcessorHyperThreadingDisable" option [Hsd-ES]:[22011580137], Increase the size of core in CPU Socket Configuration for M50CYP [Hsd-ES]:[2103639777], BIOS Version contain build time on Setup Main screen with custom BIOS revision. [Hsd-ES]:[14013449243], Whitley UEFI Firmware Flash Update Library Local Auto-Variable Address Assigned to Function Parameter [Hsd-ES]:[1509105820], Correct System event log help text as View/Configure system event log information and settings. [Hsd-ES]:[1509046234], Correct SGX comments align with RP bios [Hsd-ES]:[2103639570], Correct Processer UPI Error programming. Server-RC-0.2.2.003a ================================================================================ R01.01.0003 ================================================================================ Change BIOS ID to SE5C620.86B.01.01.0003 Merge code change to fix 2103639051: SUT will not auto power on at second T-1 state after flash BIOS recovery region via Sysfwupdt_V14_2_Build9. XCC microcode update to 0x0d000280 HSD-ES:2103639075, Current Active Processor Cores is not changed after change Active Processor Cores via syscfg HSD-ES:2103639471, BIOS version in recovery region is incorrect with R01.01.0001 on active region and 0020.P20 on recovery region. HSD-ES:1508970720, Correct the help text of PCIE Correctable Error Threshold. HSD-ES:1508946483, Use efivarstore UBA_SETUP to judge if hide USB Rear Ports Enable setup item. HSD-ES:2103639392, Correct SMBIOS type 8 data on D50TNP. HSD-ES:1508930909, Missing device definitions for NorthPeak devices in PlatformPciTree10nm asi files. HSD-ES:2103639070, Adjust the code poistion of enabling CSMI for IMC bank. HSD-ES:1508846031, Please replace BIOS RAID Option "Intel(R) RSTe" to "Intel VROC". HSD-ES:1508903189, Notify BMC when SMI update BIOS. HSD-ES:18015073494, Set the value of PcieMaxReadRequestSize to 4096B by default. HSD-ES:1508907381, it will not show any error message when user 2 name the same with user 6 name. Server-RC-0.2.2.0018